• 한국진공학회지
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• 제7권3호
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• pp.167-272
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• 1998

ECR plasma CVD를 이용한 SiOF박막은 낮은 유전상수를 가지고 있으며, 기존의 공정과의 정합성이 우수해 다층배선 공정에 채용이 유망한 재료이지만 수분의 흡수로 인한 유전율의 상승과 후속공정의 안정성이 문제점으로 부각되고 있다. 따라서 본 연구에서는 SiOF박막의 내흡습성과 후속공정에서의 안정성을 향상시키기 위하여 SiOF박막을 증착한 후 후속 산소 플라즈마 처리를 행하였다. SiOF박막은 산소 플라즈마 처리를 수행함으로써 SiOF박막의 밀도가 증가하고, 수분과의 친화력이 강한 Si-F 결합이 감소하는 것이 주요한 원인으로 사료된다. 하지만 플라즈마 처리 시간이 5분 이상으로 증가하면 유전율의 증가가 일어난다. 따라서 본 실험에서는 산소 플라즈마 처리조건이 마이크로파 전력이 700W, 공정 압력이 3mTorr, 기판온도가 $300^{\circ}C$일 경우 플라즈마 처리시간은 3분이 적당한 것으로 생각 된다.

• 전기학회논문지
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• 제61권6호
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• pp.817-820
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• 2012

We studied p-type capacitance characteristics of ZnO thin-film transistors (TFT's), grown by metal organic chemical vapor deposition (MOCVD). We compared two ZnO TFT's: one grown at $450^{\circ}C$ and the other grown at $350^{\circ}C$. ZnO grown at $450^{\circ}C$ showed smooth capacitance profile with electron density of $1.5{\times}10^{20}cm^{-3}$. In contrast, ZnO grown at $350^{\circ}C$ showed a capacitance jump when gate voltage was changed to negative voltages. Current-voltage characteristics measured in the two samples did not show much difference. We explain that the capacitance jump is related to p-type ZnO layer formed at the $SiO_2$ interface. Current-voltage and capacitance-voltage data support that p-type characteristics are observed only when background electron density is very low.

• 한국결정성장학회지
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• 제19권1호
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• pp.15-18
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• 2009

본 연구에서는 근 자외선 및 가시광 영역에서 우수한 발광 강도를 가지는 적색 형광체를 얻기 위하여 고상 반응법으로 합성하여 $EU^{3+}$와 $Bi^{3+}$가 도핑 된 ${Y_2}{SiO_5}$의 발광 특성을 관찰하였다. 근자외선 영역인 ${\lambda}_{ex}=395nm$ 기준으로 측정하였고, $^5D_0-^7F_2$의 에너지 천이에 의해 612 nm 영역에서 강한 peak가 발생하였다. CST가 $Eu^{3+}-O^{2-}$에 의해 258 nm 영역 대에서 생성되었고, $Bi^{3+}$가 함께 도핑 된 것은 $Eu^{3+}-Bi^{3+}-O^{2-}$에 상호작용에 의해 282 nm 영역대의 장파장 쪽으로 이동하였다. $350\;nm{\sim}480\;nm$ 영역 대에 '$^7F_0{\to}^5L_9$ (364 nm), $^7F_0{\to}^5G_3$(381 nm), $^7F_0{\to}^5L_6$(395nm), $^7F_0{\to}^5D_3$(415 mn) and $^7F_0{\to}^5D_2$(466 nm)는 $Bi^{3+}$와 $EU^{3+}$ f-f 천이에 의해 발생하였다. $Bi^{3+}$의 도핑농도가 증가할수록 발광 강도가 증가함을 보이다가 0.125 mol 일 때 발광강도가 가장 우수하였고, $Bi^{3+}$의 도핑 농도가 0.125 mol 이상 되면 발광강도가 현저히 감소하는 것을 확인하였다.

• Transactions on Electrical and Electronic Materials
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• 제6권1호
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• 한국세라믹학회지
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• 제40권12호
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• pp.1197-1201
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• 2003

대기 중에서 침전이 생기지 않고 코팅에 적합한 나노크기 Au 미립자가 분산된 ZrO$_2$ 용액을 제조하여, 딥-코팅법으로 SiO$_2$ 유리기판 위에 박막을 제조했다. 이 박막을 열처리하여 열분석, 엑스선 회절분석, 분광분석, 원자력간 현미경, 주사전자현미경 및 투과전자현미경 관찰 등을 통하여 박막의 특성을 조사하였다. ZrO$_2$ 박막은 50$0^{\circ}C$에서 정방정상으로 결정전이가 관찰되었고, 박막의 두께는 약 100nm였다. 분산된 입자의 크기는 약 15∼40nm이며, 표면 거칠기는 0.84nm로 우수한 막질을 나타냈다. 그리고 Au 입자의 표면플라즈마 공명에 의한 흡수피크를 630∼670nm 파장범위에서 확인할 수 있었다.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.157-158
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• 2002

A surface hardenable low alloy carbon steel was implanted with medium energy (20 - 50KeV) $N_2^+$ ions to produced a modified hardened surface. The implantation conditions were varied and are given in several doses. The surface hardness of treated and untreated steels were measured using depth sensing ultra micro indentation system (UMIS). It is shown that the hardness of nitrogen ion implanted steels varied from 20 to 50GPa depending on the implantation conditions and the doses of implantation. The structure of the modified surfaces was examined by X-ray photoelectron spectroscopy (XPS). It was found that the high hardness on the implanted surfaces was as a result of formation of non-equilibrium nitrides. High-resolution XPS studies indicated that the nitride formers were essentially C and Si from the alloy steel. The result suggests that the ion implantation provided the conditions for a preferential formation of C and Si nitrides. The combination of evidences from nano-indentation and XPS, provided a strong evidence for the existence of $sp^3$ type of bonding in a suspected $(C,Si)_xN_y$ stoichiometry. The formation of ultra hard surface from relatively cheap low alloy steel has significant implication for wear resistance implanted low alloy steels.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.200.2-200.2
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• 2013

Yttrium (Y)이 도핑 된 ZnO 나노 구조물을 수열합성법으로 제작하였다. 먼저 졸겔법으로 SiO2/Si 기판 위에 seed layer (Y-doped ZnO ; Y0.02Zn0.98O)를 제작하였으며 5번의 코팅을 진행하여 박막의 두께는 약 180 nm로 측정이 되었다. 그 후 진공 분위기에서 RTA를 이용하여 $500^{\circ}C$에서 3분간 열처리가 진행되었다. 이어서 수열합성법으로 mole 농도를 0.5~1.0 M 범위에서 변화시키며 YZO 시료를 제작하였다. X-ray diffraction (XRD)을 통해서 Y2O3 또는 결함과 관련된 피크는 관찰이 되지 않았으며, 모든 구조물에서 압축응력이 존재하는 알 수 있었으며, field emission scanning electron microscope (FESEM)에서 나노 구조물의 크기와 형태는 수열합성법의 mole 농도에 많은 영향을 받는 것으로 나타났다. Hall effect 측정을 통해서 모든 구조물은 n-type 전도 특성을 가지는 것으로 나타났다. 또한 광학적 특성인 photoluminescence (PL)에서는 수열합성법의 화학식을 고려할 때 Zn가 rich한 상태에서는 Zn interstitial로 존재하는 것으로 나타났고, mole 농도가 높아 질수록 free exciton에 의한 재결합인 UV emission이 우세하게 나타났다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.16.1-16.1
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• 2009

We have fabricated solution processed oxide semiconductor active layer for thin film transistors (TFTs). The oxide semiconductor layers were prepared by ink-jet printing the sol-gel precursor solution based on doped-ZnO. Inorganic ZnO-based thin films have drawn significant attention as an active channel layer for TFTs applications alternative to conventional Si-based materials and organic semiconducting materials, due to their wide energy band gap, optical transparency, high mobility, and better stability. However, in spite of such excellent device performances, the fabrication methods of ZnO related oxide active layer involve high cost vacuum processes such as sputtering and pulsed laser deposition. Herein we introduced the ink-jet printing technology to prepare the active layers of oxide semiconductor. Stable sol-gel precursor solutions were obtained by controlling the composition of precursor as well as solvents and stabilizers, and their influences on electrical performance of the transistors were demonstrated by measuring electrical parameters such as off-current, on-current, mobility, and threshold voltage. Microstructure and thermal behavior of the doped ZnO films were investigated by SEM, XRD, and TG/DTA. Furthermore, we studied the influence of the ink-jet printing conditions such as substrate temperature and surface treatment on the microstructure of the ink-jet printed active layers and electrical performance. The mobility value of the device with optimized condition was about 0.1-1.0 $cm^2/Vs$ and the on/off current ratio was about $10^6$. Our investigations demonstrate the feasibility of the ink-jet printed oxide TFTs toward successful application to cost-effective and mass-producible displays.

• Journal of Information Display
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• 제6권2호
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• pp.16-18
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.