• 대한전자공학회논문지SD
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• 제37권12호
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• pp.1-9
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• 2000

미세구조 N-채널 MOSFET의 게이트-소스 전압에 의존하는 유효 채널 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출을 위해서 새로운 ERM-방법을 제안하였다. ERM-방법은 선형영역에서 동작하는 게이트 길이가 다른 두개의 소자($W_m/L_m=30{\mu}m/0.6{\mu}m, 30{\mu}m/1{mu}m$)에 적용되었고 유효 채널 캐리어 이동도를 모델링하고 추출하는 과정에서 게이트-소스 전압에 의존하는 소스 및 드레인 기생저항의 영향을 고려하였다. ERM-방법으로 추출된 특성변수들을 사용한 해석적 모델식과 소자의 측정데이터를 비교해본 결과 오차가 거의 없이 일치하는 것을 확인하였다. 따라서, ERM-방법을 사용하면 대칭구조 및 비대칭구조 소자의 유효 채널 캐리어 이동도, 소스 및 드레인 기생저항과 다른 특성변수들을 정확하고 효율적으로 추출할 수 있을 것으로 기대된다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권3호
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• pp.161-166
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• 1999

We investigate the device characteristics of the separated shorted-anode LIGBT (SSA-LIGBT), which suppresses effectively the negative differential resistance regime, by 2-dimensional numerical simulation. The SSA-LIGBT increases the pinch resistance by employing the highly resistive n-drift region as an electron conduction path instead of the lowly resistive n buffer region of the conventional SA-LIGBT. The negative differential resistance regime of the SSA-LIGBT is significantly suppressed as compared with that of the conventional SA-LIGBT. The SSA-LIGBT shows the lower forward voltage drop than that of the conventional SA-LIGBT.

• 한국정보통신학회논문지
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• 제6권1호
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• pp.99-102
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• 2002

다결정 실리콘층 아래의, 게이트 산화막이라고 불리는 높은 온도에서 형성된 산화막에서 핀홀이 관찰되었으며 그 메카니즘이 분석되었다. 다결정 실리콘층 아래의 산화막은 다른 다결정 실리콘층의 플라즈마 에칭 과정 동안에 파괴되어진다. 두 개의 다결정 실리콘층은 CVD증착에 의해 만들어진 0.8$\mu\textrm{m}$의 두꺼운 산화막에 의해 분리되어 있다. 파괴된 산화막들이 아크가 발생한 부분을 중심으로 흩어져 있으며 아크가 발생한 부분에서 생성된 극도로 강한 전계가 게이트 산화막을 파괴 시켰다고 가정된다. 아크가 발생한 부분은 Alignment key에서 관찰되었고 그리고 이것이 발견된 웨이퍼는 낮은 수율을 보여주었다. 아크가 발생한 부분이 칩의 내부가 아니더라도 게이트 산화막의 파괴에 의해 칩이 정상적으로 동작하지 않았다.

• ETRI Journal
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• 제35권3호
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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• pp.110-114
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• 1990

Double Injection Switching Devices consist of $P^+$ and $n^+$ contact separated by a near intrinsic Semiconductor region containing deep trap. A V-Groove Double Injection Switching Devices were proposed for high voltage performance and Optical gating scheme. The experimental result to demonstrate the feasibility of these devices (Planar type, V-Groove type, Injection Gate mode, Optical Gate mode) for practical application are described.

• 해양환경안전학회지
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• 제2권1호
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• pp.57-65
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• 1996

The latest date, No. 1 YouII was grounded and sunk into the sea at MAMHYUNGJEDO ( South brother Island) in Sep. 21. 1995, and M.V. Sea Prince of V.L.C.C also made a big oil poullution accident owing to Typhoon "Paei" at front sea of Yeu Choun on Jul. 25. 1995. The large or small scall scale of oil poullution accident frequently was occurred about 300-350 cases per ine(1) year. The countries advanced in marine relations like as, nited Kingdom and Japan, have perfect system The country of expert education, training and oil recovery equipments in oil poullution accidents. The large quantity oil skimming ship's basic condition need general skimming ship which was high speed and large quantity skimming ability , and hve to store the recovered oil into tanks This oil skimming shop are composit the skimmer whuch move up and down according to the wace movements, storage tank which storage the recovered oil in after side, transfer pump which transformed from flooding tank to separating tank and separating tank which separated the oil mixtures, Also there are cylindrical floated which keep the auto positing, gate which keep the auto positing, gate which protect and guide the recovering oil from sea and balance weight for skimmer balance. Also there are cylindrical floated which keep the auto positing, gate which protect and guide the recovering oil from sea and balance weight for skimmer balance. The important arrangement is twin arm which moved by two hinge and move te skimming unit by wave movement. In gate of inside, made long wear in the gate bellow position, there are also connected the flexible hose for oil mixtures drop. The separating tank composited with multi-divided bulkhead for ffective oil and sea water separating by settling and flotation principle. As use the above natural princile and equipment, we can remove the large quantity oil by developed oil skimming ship.ming ship.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.653-656
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• 2003

We have designed embedded web sewer system and ported Linux operating system version 2.4.5 at our system. And then We implemented to control and monitor widely separated hardware and implemented to monitor widely separated image using CMOS image sensor HV7131B. Web server is the Boa web server with General Public License. We designed for this system using of Intel's SA1110 ARM core base processor and connecting input and output device at GPIO port of SA1110. Device driver of General purpose I/O for Embedded Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
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• pp.22-25
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• 2001

A thyristor switch circuit for capacitor discharge application, of which the equivalent circuit includes a resistor between cathode and gate of a reverse-conducting thyristor and an avalanche diode anti-parallel between its anode and gate to set thyristor tum-on voltage, is monolithically integrated by planar process with AVE double-implantation method. To ensure a lower breakdown voltage of the avalanche diode for thyristor tum-on than the break-over voltage of the thyristor, $p^+$ wells on thyristor p base layer are made by boron implantation/drive-in for a steeper doping profile with higher concentrations while rest p layers of thyristor and free-wheeling diode parts are formed with Al implantation/drive-in for a doping profile of lower steepness. The free-wheeling diode part is isolated from the thyristor part by formation of separated p-well emitter for suppressing commutation between them, which is achieved during the formation of thyristor p-base layer.

• ETRI Journal
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• 제37권6호
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• 한국자동차공학회논문집
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• 제23권1호
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• pp.25-33
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• 2015

This paper presents the d-q axis equivalent circuit model of an interior permanent magnet (IPM) which includes the iron loss resistance. The model is implemented to be able to run in real-time on the FPGA-based HIL simulator. Power electronic devices are removed from the motor control unit (MCU) and a separated controller is interfaced with the real-time simulated motor drive through a set of proper inputs and outputs. The inputs signals of the HIL simulation are the gate driver signals generated from the controller, and the outputs are the winding currents and resolver signals. This paper especially presents iron loss prediction which is introduced by means of comparing the torque calculated from d-q axis currents and the desired torque; and minimizing the torque difference. This prediction method has stable prediction algorithm to reduce torque difference at specific speed and load. Simulation results demonstrate the feasibility and effectiveness of the proposed methods.