• Journal of the Semiconductor & Display Technology
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• v.8 no.1
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• pp.1-5
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• 2009

Typically, single-wafer wet etching is done by dispensing chemical onto the front and back side of spin wafer. The wafer is fixed by a number of chuck pins, which obstruct the chemical flow and would result in the incomplete removal of the remaining film, which can become a source of contamination in the next process. In this paper, we introduce a novel design of wafer chuck, in which chuck pins are groupped into two and each group of pins fixes the substrate alternatively. Two groups of chuck pins fix the high-speed spin substrate with non contact method using a magnetic material. The actual process has been executed to observe the effectiveness of this new wafer chuck. It was found that the new wafer chuck performed better than the conventional wafer chuck for removing the remaining film from the bevel and edge side of substrate.

• Journal of the Semiconductor & Display Technology
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• v.2 no.3
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• pp.31-36
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• 2003

On this study, an E.E(End-Effector) for the 300 mm wafer transfer robot system is newly suggested. It is a mechanical type with $180^{\circ}$ rotating ranges and is composed of 3-point arms, two plate springs and single-axis DC motor controlled by microchip. To design, relationship between the gripping force and the wafer deformation is analyzed by FEM. By analytic results, the gripping force for 300 mm wafer is confirmed as 255~274 gf. From experimental results on gripping force, repeatable position accuracy and gripping cycle times in a wafer cleaning system, we confirmed that the suggested E.E was well designed to satisfiy on the required performance for 300 mm wafer transfer robot system.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.6
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• pp.486-491
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• 2000

The dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using neural network in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, five features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision, back-propagation neural network is adopted to classify the dicing process into normal and abnormal dicing, and normal and damaged blade. Experiments have been performed for GaAs semiconductor wafer in the case of normal/abnormal dicing and normal/damaged blade. Based upon observation of the experimental results, the proposed scheme shown has a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 6.5%.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• Journal of Industrial Technology
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• v.43 no.1
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• pp.49-55
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• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.2
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.18 no.1
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• pp.1-12
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• 2009

Presently, the semiconductor industry has the chronic problem. In the semiconductor industry, it has the semiconductor wafer, a package, the optical filter cut by using the saw blade, the mold, a laser etc. The cutting technique has the difficulty due to the rising of the production cost by the wearing of mold, the poor quality problem due to generated heat at the moment of cutting procedure and curve cutting etc. The goal of this time of national research and development project is develop the apparatus for solving the problem that the existing cutting technique has. The technology is so called waterjet abrasive method. This technology will be mainly applied to cut a semiconductor package and a wafer. Two important things to be considered are ripple effect(in other words, the scale of a market) and simplicity of an application.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.72-77
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• 2016

As the semiconductor production technology has gradually developed and intra-market competition has grown fiercer, the caliber of Si Wafer for semiconductor production has increased as well. And semiconductors have become integrated with higher density. Presently the Si Wafer caliber has reached up to 450 mm and relevant production technology has been advanced together. Electrostatic chuck is an important device utilized not only for the Wafer transport and fixation but also for the heat treatment process based on plasma. To effectively control the high calories generated by plasma, it employs a refrigerant-based cooling method. Amid the enlarging Si Wafers and semiconductor device integration, effective temperature control is essential. Therefore, uniformed temperature distribution in the electrostatic chuck is a key factor determining its performance. In this study, the form of refrigerant flow channel will be investigated for uniformed temperature distribution in electrostatic chuck.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.142-147
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• 2022

After introducing Hybrid Bonding technology into image sensors using stacked sensors and image processors, large quantity production became possible. As a result, it is currently used in most of the CMOS image market in smartphones and other image-based devices worldwide, and almost all stacked CIS manufacturing sites have focused on miniaturization using hybrid bonding. In this study, an upper wafer handling module for Wafer to Wafer Hybrid Bonding developed to increase the alignment and precision between wafers when wafer bonding. The module was divided two parts to reduce error of both the alignment and degree of precision during wafer bonding. Wafer handling module developed both new Tip/Tilt system controlling θx,θy of upper wafer and striker to push upper wafer. Based on this, it was confirmed through the stability evaluation that the upper wafer handling module can be controlled without any problem during W2W hybrid bonding.