• Title/Summary/Keyword: Semiconductor package

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Wafer Level Package Design Optimization Using FEM (공정시간 및 온도에 따른 웨이퍼레벨 패키지 접합 최적설계에 관한 연구)

  • Ko, Hyun-Jun;Lim, Seung-Yong;Kim, Hee-Tea;Kim, Jong-Hyeong;Kim, Ok-Rae
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.23 no.3
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    • pp.230-236
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    • 2014
  • Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and fracture are major concerns for semiconductor manufacturing. We optimized the wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and prevents the filling material from overflowing. In this study, finite element analysis was employed to determine the key factors that may affect the reliability performance of the dam package. Three-dimensional finite element models were constructed using the simulation software ANSYS to perform the dam thermo-mechanical simulation and analysis.

Cure Characteristics of Naphthalene Type Epoxy Resins for SEMC (Sheet Epoxy Molding Compound) for WLP (Wafer Level Package) Application (WLP(Wafer Level Package)적용을 위한 SEMC(Sheet Epoxy Molding Compounds)용 Naphthalene Type Epoxy 수지의 경화특성연구)

  • Kim, Whan Gun
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.1
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    • pp.29-35
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    • 2020
  • The cure characteristics of three kinds of naphthalene type epoxy resins(NET-OH, NET-MA, NET-Epoxy) with a 2-methyl imidazole(2MI) catalyst were investigated for preparing sheet epoxy molding compound(SEMC) for wafer level package(WLP) applications, comparing with diglycidyl ether of bisphenol-A(DGEBA) and 1,6-naphthalenediol diglycidyl ether(NE-16) epoxy resin. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The NET-OH epoxy resin represented an n-th order cure mechanism as like NE-16 and DGEBA epoxy resins, however, the NET-MA and NET-Epoxy resins showed an autocatalytic cure mechanism. The NET-OH and NET-Epoxy resins showed higher cure conversion rates than DGEBA and NE-16 epoxy resins, however, the lowest cure conversion rates can be seen in the NET-MA epoxy resin. Although the NETEpoxy and NET-MA epoxy resins represented higher cure reaction conversions comparing with DGEBA and NE-16 resins, the NET-OH showed the lowest cure reaction conversions. It can be figured out by kinetic parameter analysis that the lowest cure conversion rates of the NET-MA epoxy resin are caused by lower collision frequency factor, and the lowest cure reaction conversions of the NET-OH are due to the earlier network structures formation according to lowest critical cure conversion.

Evaluation of ENEPIG Surface Treatment for High-reliability PCB in Mobile Module

  • Lee, Joon-Kyun;Yim, Young-Min;Seo, Jun-Ho
    • Journal of the Korean institute of surface engineering
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    • v.43 no.3
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    • pp.142-147
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    • 2010
  • We evaluated characteristics of ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) surface treatment for mobile equipment that requires high reliability, in addition to investigating surface treatment processes for semiconductor boards that require high reliability such as regular PCB-package systems, board-on-chip, chip-scaled package (CSP), etc and application for semiconductor package board of SIP, BOC. As a result, it appeared that ENEPIG has superior properties compared to ENIG surface treatment in corrosion resistance, solder junction, wetting, etc. We anticipate that these results will be able to lend credibility to ENEPIG as a low-cost alternative for producing mobile devices such as the cell phones, especially when applied to mass production.

A Case-based Decision Support Model for The Semiconductor Packaging Tasks

  • Shin, Kyung-shik;Yang, Yoon-ok;Kang, Hyeon-seok
    • Proceedings of the Korea Inteligent Information System Society Conference
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    • 2001.01a
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    • pp.224-229
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    • 2001
  • When a semiconductor package is assembled, various materials such as die attach adhesive, lead frame, EMC (Epoxy Molding Compound), and gold wire are used. For better preconditioning performance, the combination between the packaging materials by studying the compatibility of their properties as well as superior packaging material selection is important. But it is not an easy task to find proper packaging material sets, since a variety of factors like package design, substrate design, substrate size, substrate treatment, die size, die thickness, die passivation, and customer requirements should be considered. This research applies case-based reasoning(CBR) technique to solve this problem, utilizing prior cases that have been experienced. Our particular interests lie in building decision support model to aid the selection of proper die attach adhesive. The preliminary results show that this approach is promising.

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Performance Advancement of Evaluation Algorithm for Inner Defects in Semiconductor Packages (반도체 패키지 내부결함 평가 알고리즘의 성능 향상)

  • Kim, Chang-Hyun;Hong, Sung-Hun;Kim, Jae-Yeol
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.15 no.6
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    • pp.82-87
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    • 2006
  • Availability of defect test algorithm that recognizes exact and standardized defect information in order to fundamentally resolve generated defects in industrial sites by giving artificial intelligence to SAT(Scanning Acoustic Tomograph), which previously depended on operator's decision, to find various defect information in a semiconductor package, to decide defect pattern, to reduce personal errors and then to standardize the test process was verified. In order to apply the algorithm to the lately emerging Neural Network theory, various weights were used to derive results for performance advancement plans of the defect test algorithm that promises excellent field applicability.

A Multi-Level Knowledge-Based Design System for Semiconductor Chip Encapsulation

  • Huh, Y.J.
    • Journal of the Microelectronics and Packaging Society
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    • v.9 no.1
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    • pp.43-48
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    • 2002
  • Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

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Recent Overview on Power Semiconductor Devices and Package Module Technology (차세대 전력반도체 소자 및 패키지 접합 기술)

  • Kim, Kyoung-Ho;Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.26 no.3
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    • pp.15-22
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    • 2019
  • In these days, importance of the power electronic devices and modules keeps increasing due to electric vehicles and energy saving requirements. However, current silicon-based power devices showed several limitations. Therefore, wide band gap (WBG) semiconductors such as SiC, GaN, and $Ga_2O_3$ have been developed to replace the silicon power devices. WBG devices show superior performances in terms of device operation in harsh environments such as higher temperatures, voltages and switching speed than silicon-based technology. In power devices, the reliability of the devices and module package is the critically important to guarantee the normal operation and lifetime of the devices. In this paper, we reviewed the recent trends of the power devices based on WBG semiconductors as well as expected future technology. We also presented an overview of the recent package module and fabrication technologies such as direct bonded copper and active metal brazing technology. In addition, the recent heat management technologies of the power modules, which should be improved due to the increased power density in high temperature environments, are described.

A Study on Measurement of Semiconductor Package in RF Regime (RF대역에서의 반도체 package 특성 측정에 관한 연구)

  • 박현일;김기혁;황성우
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.108-111
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    • 2000
  • The electrical characteristics of MQFP packages have been measured in RF regime. The s-parameter of the lead frame has been measured using the test fixture on which the do-capped package was mounted. A simple lumped equivalent circuit modeling of the lead frame and the test fixture can provide reasonable model parameters up to the frequency of 200 MHz.

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High Integration Packaging Technology for RF Application

  • Lee, Young-Min
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 1999.12a
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    • pp.127-154
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    • 1999
  • Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

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