• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.543-546
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• 2001

So far, the design methods of quartz crystal resonator have been developed. Recently, as the electronic package and semiconductor modules become smaller, the need to minimize the sizes of crystal components grows larger. but Minimizing crystal plate sizes has limitations because its temperature-frequency characteristics is worse and unwanted resonances occur. so appropriate design of electrode size and crystal plates is necessary. In this palter, Two-dimensional governing equations for electroded piezoelectric crystal plates with general symmetry have been solved from deduced equations from three-dimensional equations of linear piezoelectricity in most cases. In practice, electroded piezoelectric crystal plates have three-dimensional geometry, so simplified 2-dimensional equations and 2-D modeling are insufficient for explaining its resonance modes and characteristics. So, three-dimensional FEM(finite element method) analysis is done and its effectiveness is verified from analyzing practical crystal resonator model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.259-262
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• 2013

Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

• Laser Solutions
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• v.11 no.1
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• pp.7-11
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• 2008

Decapsulation technology is useful to inspect EMC of package device and the etching technology enable to check inside of device by removing plastic molding. Chemical etching method is used widely to fabricate a lot of semiconductor. But the method has some disadvantage due to wet process. Proposed method in this paper shows the application possibility such as fast processing time, processing accuracy and dry process. These result was obtained by directly removing of packed EMC using UV laser.

• Applied Science and Convergence Technology
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• v.23 no.4
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• pp.169-178
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• 2014

Fluid model based numerical analysis is done to simulate a low damage etch back system for 20 nm scale semiconductor fabrication. Etch back should be done conformally with very high material selectivity. One possible mechanism is three steps: reactive radical generation, adsorption and thermal desorption. In this study, plasma generation and transport steps are analyzed by a commercial plasma modeling software package, CFD-ACE+. Ar + $CF_4$ ICP was used as a model and the effect of reactive gas inlet position was investigated in 2D and 3D. At 200~300 mTorr of gas pressure, separated gas inlet scheme is analyzed to work well and generated higher density of F and $F_2$ radicals in the lower chamber region while suppressing ions reach to the wafer by a double layer conducting barrier.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.9
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• pp.899-905
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• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as Scratch, Flash, Resin bleed, and Melting. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, Resin bleed and Melting are the most difficult ones to classify accurately. The brightness value and the shape of Resin bleed and Melting defects are so similar that normally it is difficult to classify the Resin bleed and Melting. In this paper, we propose a segmenting method and a set of features for detecting and classifying the Resin bleed and Melting defects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.577-595
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• 2017

${\bullet}$ Silicon Carbide (SiC) had excellent material properties as the base material for next generation of power semiconductor. In developing SiC MOSFET, gate oxide reliability issues had to be first overcome before commercial application. Besides, a high and stable gate-source voltage threshold $V_{GS(th)}$ is also an important parameter for operation robustness. SiC MOSFET with such characteristics can directly use existing high-speed IGBT gate driver IC's. ${\bullet}$ The linear voltage drop characteristics of SiC MOSFET will bring lower conduction loss averaged over full AC cycle compared to similarly rate IGBT. Lower switching loss enable higher switching frequency. Using package with auxiliary source terminal for gate driving will further reduce switching losses. Dynamic characteristics can fully controlled by simple gate resistors. ${\bullet}$ The low switching losses characteristics of SiC MOSFET can substantially reduce power losses in high switching frequency operation. Significant power loss reduction is also possible even at low switching frequency and low switching speed. in T-type 3-level topology, SiC MOSFET solution enable three times higher switching freqeuncy at same efficiency.

• Journal of Surface Science and Engineering
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• v.55 no.5
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• pp.299-307
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• 2022

Gold plating is used as a coating of connector in printed circuit boards, ceramic integrated circuit packages, semiconductor devices and so on, because the film has excellent electric conductivity, solderability and chemical properties such as durability to acid and other chemicals. In most cases, internal connection between device and package and external terminals for connecting packaging and printed circuit board are electroless Ni-P plating followed by immersion Au plating (ENIG) to ensure connection reliability. The deposition behavior and film properties of electroless Au plating are affected by P content, grain size and mixed impurity components in the electroless Ni-P alloy film used as the underlayer plating. In this study, the correlation between electroless nickel plating used as a underlayer layer and cyanide-free electroless Au plating using thiomalic acid as a complexing agent and aminoethanethiol as a reducing agent was investigated.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.417-420
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• 2010

반도체 패키지 제조공정 중에는 제품에 일련번호를 인쇄하는 마킹공정이 있다. 마킹 공정에서 새겨진 문자는 해당 관리기준에 따라 관리되고 있는데 최근 반도체 패키지의 소형화에 따라 인쇄된 마크문자의 틀어짐 정도가 관리기준에 미달되는 문제가 발생되고 있다. 본 논문에서는 마크문자의 검사 항목 중 tilted mark(angle mark) 검사를 위한 회전량 측정방법으로 golden section searching 방법을 적용한 고속 라돈 변환(radon transform)방법을 제안한다. 실험에서는 제안한 방법이 일반적인 라돈 변환에 비해 최대 약 21 배의 회전량 측정속도가 향상되는 것을 확인하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1034-1046
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• 2013

In this paper, a design of a GaN HEMT power amplifier using output matching circuit with arbitrary harmonic impedances is presented. The adopted GaN HEMT device, TGF2023-02 of TriQuint Semiconductor, was packaged in commercial package. The optimal impedances of the GaN HEMT package are extracted from load-pull simulation at package input and output reference planes. The targets of load-pull simulation are the highest output power at fundamental frequency and the highest efficiency at $2^{nd}$ and $3^{rd}$ harmonic frequencies. Because of fixture in the package, the extracted impedances shows arbitrary harmonic impedances. In order to match the optimal impedances, output matchin circuit which has 4 transmission lines is presented. Characteristic impedances and electrical lengths of the transmission lines are mathmatically calculated. The power amplfiier with $54.6{\times}40mm^2$ shows the output power of 8 W at the fundamental frequency of 2.5 GHz, the efficiency above 55 %, and harmonic suppression of above 35 dBc at the $2^{nd}$ and the $3^{rd}$ harmonics.