Efficient Multi-site Testing Using ATE Channel Sharing |
Eom, Kyoung-Woon
(Dept. of Electrical & Electronic Eng., Yonsei University)
Han, Dong-Kwan (Dept. of Electrical & Electronic Eng., Yonsei University) Lee, Yong (Dept. of Electrical & Electronic Eng., Yonsei University) Kim, Hak-Song (Dept. of Electrical & Electronic Eng., Yonsei University) Kang, Sungho (Dept. of Electrical & Electronic Eng., Yonsei University) |
1 | Rivoir, Jochen, "Parallel Test Reduces Cost of Test More Effectively Than Just a Cheap Tester", Proc. of Electronics Manufacturing Technology Symposium, 2004, pp. 263-272. |
2 | Schneider, B and Oestergaard, P, "An Advanced Data Compaction Approach for Test-During Burnin", Proc. of ITC 1988, p 381. |
3 | Goel S. K., Marinissen E. J., "Optimisation of onchip design-for-test infrastructure for maximal multi-site test throughput", IET Proc. of Computers and Digital Techniques, May 2005, pp. 442-456. |
4 | Yasuhiro Mabuchi, Test Faciliation Circuit, US 2003/0233606 A1, http://patft.uspto.gov/ |
5 | Arslan, B. Orailoglu, A. "Adaptive Test Optimization through Real Time Learning of Test Effectiveness", Proc.of DATE, 2011. |
6 | Semiconductor Industry Association (SIA), ITRS 2010. |