• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

• Bulletin of the Korean Chemical Society
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• 제28권6호
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• pp.921-928
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• 2007

Three different phosphonated trisbipyridine ruthenium complexes, [(4-CH3-4'-CH2PO(OH)2-2,2'-bipyridine)- (bpy)2Ru]·(PF6)2 (Ru-P1), [(4-CH3-4'-CH2PO(OH)2-2,2'-bipyridine)3Ru]·(PF6)2 (Ru-P2), and [(4,4'-CH2PO- (OH)2-2,2'-bipyridine)3Ru]·(PF6)2 (Ru-P3) were synthesized and their photochemical and electrochemical properties were studied. These ruthenium complexes were strongly adsorbed on the surface of the layered metal oxide semiconductor K4Nb6O17 that was partially acid-exchanged and sensitized up to pH 10, while the carboxylated ruthenium complex, (4,4'-COOH-2,2'-bipyridine)3Ru·Cl2 (Ru-C) that was previously studied was sensitized only below pH 4. The visible light water reduction at K4Nb6O17 that was internally platinized and sensitized by these phosphonated Ru-complexes was comparatively studied using a reversible electron donor iodide.

• 진공이야기
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• 제5권2호
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• pp.10-17
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• 2018

Chalcogenide and oxide heterostructures have been studied as a next-generation electronic materials, due to their interesting electronic properties, such as direct bandgap semiconductor, ferroelectricity, ferromagnetism, superconductivity, charge-density waves, and metal-insulator transition, and their modification near heterointerfaces, so called, electronic reconstruction. An angle-resolved photoemission spectroscopy (ARPES) is a powerful technique to unveil such novel electronic phases in detail, especially combined with high quality thin film preparation methods, such as, molecular beam epitaxy and pulsed laser deposition. In this article, the recent ARPES results in chalcogenide and oxide thin films will be introduced.

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

• 전기전자학회논문지
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• 제15권2호
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• pp.143-148
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• 2011

MOS (Metal-Oxide Semconductor) devices among the most sensistive of all semiconductors to radiation, in particular ionizing radiation, showing much change even after a relatively low dose. The necessity of a radiation dosimeter robust enough for the working environment has increased in the fields of aerospace, radio-therapy, atomic power plant facilities, and other places where radiation exists. The power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) has been tested for use as a gamma radiation dosimeter by measuring the variation of threshold voltage based on the quantity of dose, and a maximum total dose of 30 krad exposed to a $^{60}Co$ ${\gamma}$-radiation source, which is sensitive to environment parameters such as temperature. The gate oxide structures give the main influence on the changes in the electrical characteristics affected by irradiation. The variation of threshold voltage on the operating temperature has caused errors, and needs calibration. These effects can be overcome by adjusting gate oxide thickness and implanting impurity at the surface of well region in MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.32-40
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• 2004

An extension of the density-gradient model to include the non-local transport effect is presented. The governing equations can be derived from the first three moments of the Wigner distribution function with some approximations. A new nonlinear discretization scheme is applied to the model to reduce the discretization error. We also developed a new boundary condition for the $Si/SiO_2$ interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. We report the simulation results of a 25-nm metal-oxide-semiconductor field-effect transistor (MOSFET) device.

• 센서학회지
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• 제27권3호
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• pp.160-164
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• 2018

In this paper, a wide dynamic range complementary metal-oxide-semiconductor (CMOS) image sensor with the adjustable sensitivity by using cascode metal-oxide-semiconductor field-effect transistor (MOSFET) and inverter is proposed. The characteristics of the CMOS image sensor were analyzed through experimental results. The proposed active pixel sensor consists of eight transistors operated under various light intensity conditions. The cascode MOSFET is operated as the constant current source. The current generated from the cascode MOSFET varies with the light intensity. The proposed CMOS image sensor has wide dynamic range under the high illumination owing to logarithmic response to the light intensity. In the proposed active pixel sensor, a CMOS inverter is added. The role of the CMOS inverter is to determine either the conventional mode or the wide dynamic range mode. The cascode MOSFET let the current flow the current if the CMOS inverter is turned on. The number of pixels is $140(H){\times}180(V)$ and the CMOS image sensor architecture is composed of a pixel array, multiplexer (MUX), shift registers, and biasing circuits. The sensor was fabricated using $0.35{\mu}m$ 2-poly 4-metal CMOS standard process.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.