• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.194-199
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• 1997

When voltage or current gets out of the magnetic sensor as it is, we have often faced the problems such as introduction of noise and loss of voltage. In order to reduce these problems, a 2 drain MAGFET operating in the saturation region and fabricated by CMOS process, the system of I/V converter, VCO with operational amplifier, and V/F conversion circuits with Schmitt Trigger are designed and fabricated in one package. The absolute sensitivity of magnetic sensor shows 1.9 V/T and the product sensitivity is $3.2{\times}10^{4}\;V/A{\cdot}T$. The characteristic of V/F conversion is very stabilized and has the value of 190 kHz/T.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.260-263
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• 2003

When ICP(Inductive Coupled Plasma type etching and wafer manufacturing is being processed in semiconductor process, a noxious gas in PFC and CFC system is generated. Gas cleaning dry scrubber is to remove this noxious gas. This paper describes a power source device, 2MHz switching frequency class 2kW RF Generator, used as a main power source of the gas cleaning dry scrubber. The power stage of DC/DC converter is consist of full bridge type converter with 100kHz switching frequency Power amplifier is push pull type inverter with 2MHz switching frequency, and transmission line transformer. The adequacy of the circuit type and the reliability of generating plasma in various load conditions are verified through 50$\Omega$ dummy load and chamber experiments result.

• Korean Journal of Optics and Photonics
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• v.14 no.4
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• pp.454-459
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• 2003

We report the first demonstration of 10 Gb/s wavelength conversion in a Mach-Zehnder interferometric wavelength converter monolithically integrated with a loss-coupled DFB probe source. The integrated device is fabricated using a BRS (buried ridge stripe) structure with an undoped InP clad layer on the top of a passive waveguide to reduce high propagation loss. The device exhibited a static extinction ratio of 11 dB. Good performance at 10 Gb/s is obtained with an extinction ratio of 7 dB and a power penalty of 2.8 dB at a 10$^{-9}$ bit error rate.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.1
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• pp.123-128
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• 2010

We have investigated the properties of the novel triangular ring resonator with the total internal reflection mirrors and the semiconductor optical amplifier for photonic integrated circuits (PIC). A novel triangular resonators containing active and passive sections are fabricated and characterized with various multimode interference (MMI) lengths. The optimum MMI length and width turn out to be 108 and 9 ${\mu}m$, respectively. A free spectral range of approximately 228 GHz is observed near 1558 nm along with an on-off ratio of 9 dB. The proposed triangular resonator has a good advantage to remove the direct coupling between the two access waveguides of the MMI coupler. Hence, such resonators can be directly integrated with other devices making compact and highly functional PIC possible.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.448-452
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• 2007

Many industrial operations require continuous or nearly-continuous operation of machines, which if interrupted can result in significant financial loss. The condition monitoring of these machines has received considerable attention recent years. Rapid developments in semiconductor, computing, and communication with a remote site have led to a new generation of sensor called "smart" sensors which are capable of wireless communication with a remote site. The purpose of this research is the development of smart sensor using which can on-line perform condition monitoring. This system is addressed to detect conditions that may lead to equipment failure when it is running. Moreover it will reduce condition monitoring expense using low cost MEMS accelerometer. This sensor can receive data in real-time or periodic time from MEMS accelerometer. Furthermore, this system is capable for signal preprocessing task (High Pass Filter, Low Pass Filter and Gain Amplifier) and analog to digital converter (A/D) which is controlled by CPU. A/D converter that converts 10bit digital data is used. This sensor communicates with a remote site PC using TCP/IP protocols. Wireless LAN contain IEEE 802.11i-PSK or WPA (PSK, TKIP) encryption. Developed sensor executes performance tests for data acquisition accuracy estimations.

• Korean Journal of Optics and Photonics
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• v.20 no.3
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• pp.189-194
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• 2009

We demonstrate a ring type wavelength swept laser incorporating a fiber Fabry-Perot tunable filter in a laser cavity using 1300 nm semiconductor optical amplifier as a gain medium. The output characteristics of the wavelength swept laser according to the applied scanning frequencies are analyzed in the temporal and spectral domain. The output of the wavelength swept laser decreases dramatically as the scanning frequency increases. And there is a significant peak power imbalance between the forward scan and the backward scan as the scanning frequency increases. Its use in practical applications might be limited.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.28-35
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• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.20-27
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• 2007

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.