• Journal of Applied Reliability
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• v.7 no.1
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• pp.23-29
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• 2007

Probe card is a test component which is to classify the known good die with electrical contact before the packaging in the ATE (automatic testing equipment). Conventional probe tip was mostly needle type, it has been difficult to meet with conventional type, because of decreasing chip size, pad to pad pitch and pads size increasingly. For that reason, probe cards using MEMS (micro electro mechanical system) technology have been developed for various semiconductor chips. In this paper, Area Array type MEMS Probe tip was designed,, fabricated, and characterized its mechanical and electrical properties. The authors found that good electrical characteristics under $1{\Omega}$ were acquired with gold (Au) and aluminium (Al) pad contact test over 0.5gf and 4gf respectively. And, contact resistance variation under $0.1{\Omega}$ were achieved with 100,000 times of repetition test. And, insertion loss (IS) for high frequency operation was ascertained over 300MHz at -3dB loss.

• Journal of the Korean institute of surface engineering
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• v.46 no.1
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• pp.22-28
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• 2013

$WS_2$ particles were added to micro-diamond blades with Cu/Sn binding metal as lubricants to improve cutting efficiency. It was found in previous works that the added $WS_2$ lubricant could reduce remarkably the momentary energy consumption during dicing tests but increased wear rate slightly owing to weak bonding between lubricant particles and bond metals. In the present work, the surface of $WS_2$ lubricant particles were etched for activating the surface of $WS_2$ particles that provide even distribution of particles during powder mixing process and improvement of wetting at the interfaces between $WS_2$ particles and molten Cu/Sn bond metals during pressurized sintering so that could provide the improved strength of micro-blades and result in extended life. Chipping behavior of workpiece with the types of micro-blades including $WS_2$ were compared because it is important in semiconductor and micro-packaging industries to control average roughness and straightness of sliced surface which is closely related with quality.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Korean institute of surface engineering
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• v.36 no.1
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• pp.74-78
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• 2003

The corrosion failure of electronic devices has been a major reliability concern lately. This failure is an ongoing concern because of miniaturization of integrated circuits (IC) and the increased use of polymers in electronic packaging. Recently, plasma-polymerized cyclohexane films were considered as a possible candidate for a interlayer dielectric for multilever metallization of ultra large scale integrated (ULSI) semiconductor devices. In this paper the protective ability of above films as a function of deposition temperature and RF power in an 3.5 wt.% NaCl solution were examined by polarization measurement. The film was characterized by FTIR spectroscopy and contact angle measurement. The protective efficiency of the film increased with increasing deposition temperature and RF power, which induced the higher degree of cross-linking and hydrophobicity of the films.

• Polymer Science and Technology
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• v.26 no.1
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• pp.40-46
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• 2015

• Journal of Practical Engineering Education
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• v.15 no.1
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• pp.209-221
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• 2023

In the external inspection and packaging stages of products used in the semiconductor manufacturing process, there is a problem in which particles are adsorbed to the product itself or a carrying tool due to electrostatic discharge. This study presents a methodology that can improve the problem of adsorption of particles to a product by using a practical TRIZ technique. By applying the proposed practical TRIZ-based methodology, the problem was defined, and contradictions caused by product waiting time were derived. Among the derived contradictions, physical contradictions were set and the concept of 'space separation' was applied to derive solutions such as 'installation of Ionizer' and 'improvement of the layout of the workroom'. As a result of the experiment by applying 'Ionizer Installation' and 'Workroom Layout Improvement' derived through the application of practical TRIZ, it was confirmed that the particle adsorption problem that occurs during the waiting time of the product can be solved.Through this study, it is expected that workers, facility engineers, and technical engineers working at manufacturing processes will be able to effectively solve the problems they face through creative thinking and change of ideas by using practical TRIZ techniques, and contribute to innovative technology development and productivity improvement.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.59-63
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• 2017

The n-type GaN semiconductor has excellent properties as a photoelectrode, but it has disadvantage that its reliability is deteriorated due to the photocorrosion because the oxygen reaction occurs on the surface. For this reason, there are fundamental attempts to avoid photocorrosion reaction of GaN surfaces by using the p-type GaN as a photoelectrode where hydrogen generation reaction occurs on the surface. However, p-type GaN has a problem of low efficiency because of its high resistivity and low hole mobility. In this study, we try to improve the photocurrent efficiency by activation process for the p-type GaN. The p-type GaN was annealed for 1 min. at $500^{\circ}C$ in $N_2$ atmosphere. Hall effect measurement system was used for the electrical properties and potentiostat (PARSTAT4000) was used to measure the photoelectrochemical (PEC) characteristics. Consequently, the photocurrent density was improved more than 1.5 times by improving the activation process for the p-type GaN. Also, its reliability was maintained for 3 hours.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.39-46
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• 2017

This paper presents the fabrication of ceramic insulation layer on metallic heat spreading substrate, i.e. an insulated metal substrate, for planar type heater. Aluminum alloy substrate is preferred as a heat spreading panel due to its high thermal conductivity, machinability and the light weight for the planar type heater which is used at the thermal treatment process of semiconductor device and display component manufacturing. An insulating layer made of ceramic dielectric film that is stable at high temperature has to be coated on the metallic substrate to form a heating element circuit. Two technical issues are raised at the forming of ceramic insulation layer on the metallic substrate; one is delamination and crack between metal and ceramic interface due to their large differences in thermal expansion coefficient, and the other is electrical breakdown due to intrinsic weakness in dielectric or structural defects. In this work, to overcome those problem, selected metal oxide buffer layers were introduced between metal and ceramic layer for mechanical matching, enhancing the adhesion strength, and multi-coating method was applied to improve the film quality and the dielectric breakdown property.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.