• ETRI Journal
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• v.36 no.3
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• pp.343-351
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• 2014

For the fine-pitch application of flip-chip bonding with semiconductor packaging, fluxing and hybrid underfills were developed. A micro-encapsulated catalyst was adopted to control the chemical reaction at room and processing temperatures. From the experiments with a differential scanning calorimetry and viscometer, the chemical reaction and viscosity changes were quantitatively characterized, and the optimum type and amount of micro-encapsulated catalyst were determined to obtain the best pot life from a commercial viewpoint. It is expected that fluxing and hybrid underfills will be applied to fine-pitch flip-chip bonding processes and be highly reliable.

• Journal of the Korean Applied Science and Technology
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• v.26 no.4
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• pp.379-384
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• 2009

Epoxy resin based encapsulants are widely used in semiconductor packaging applications. Epoxy resin based encapsulants are often subject to crack or delamination during the reliability test due to the thermal stress caused by high modulus nature of epoxy resins. Epoxy functional siloxanes are often added into epoxy resin to reduce the modulus so that the thermal stress can be reduced. Epoxy functional siloxanes, additives for reduced modulus, were synthesized and added into the curable epoxy resins. The modulus and the coefficient of thermal expansion (CTE) were also measured to investigate the thermal stress and to see whether the epoxy functional siloxane adversely affects the CTE or not. As a result, around 26% to 72% of thermal stress reduction was observed with no adverse effect on CTE.

• Polymer Science and Technology
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• v.24 no.1
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• pp.10-16
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• 2013

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.4
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• pp.592-597
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• 2015

3D-IC is a novel semiconductor packaging technique stacking dies to improve the performance as well as the overall size. TSV is ideal for 3D-IC because it is convenient for stacking and excellent in electrical characteristics. However, due to high-density and micro-size of TSVs, they should be tested with a non-invasive manner. Thus, we introduce a TSV test method on test prober without a direct contact in this paper. A capacitive coupling effect between a probe tip and TSV is used to discriminate small TSV faults like voids and pin-holes. Through EM simulation, we can verify the size of eye-patterns with various frequencies is good for TSV test tools and non-contact test will be promising.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.377-378
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• 2006

Thermal management technology is a critical element in all new chip generations, caused by a power multiplication combined with a size reduction. A heat sink, mounted on a base plate, requires the use of special materials possessing both high thermal conductivity (TC) and a coefficient of thermal expansion (CTE) that matches semiconductor materials as well as certain packaging ceramics. In this study, nano tungsten coated copper powder has been developed with a wide range of compositions, 90W-10Cu to 10W-90Cu. Powder technologies were used to make samples to evaluate density, TC, and CTE. Measured TC lies among theoretical values predicted by several existing models.

• Journal of the Korean institute of surface engineering
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• v.55 no.5
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• pp.299-307
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• 2022

Gold plating is used as a coating of connector in printed circuit boards, ceramic integrated circuit packages, semiconductor devices and so on, because the film has excellent electric conductivity, solderability and chemical properties such as durability to acid and other chemicals. In most cases, internal connection between device and package and external terminals for connecting packaging and printed circuit board are electroless Ni-P plating followed by immersion Au plating (ENIG) to ensure connection reliability. The deposition behavior and film properties of electroless Au plating are affected by P content, grain size and mixed impurity components in the electroless Ni-P alloy film used as the underlayer plating. In this study, the correlation between electroless nickel plating used as a underlayer layer and cyanide-free electroless Au plating using thiomalic acid as a complexing agent and aminoethanethiol as a reducing agent was investigated.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.31-37
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• 2017

Recently, there has been substantial interest in flexible and wearable devices whose properties and performances are close to conventional devices on hard substrates. Despite the advancement on flexible devices with organic semiconductors or carbon nanotube films, their performances are limited by the carrier scattering at the molecular to molecular or nanotube-to-nanotube junctions. Here in this study, we demonstrate on the vertical semiconductor crystal array embedded in flexible polymer matrix. Such structures can relieve the strain effectively, thereby accommodating large flexural deformation. To achieve such structure, we first established a low-temperature solution-phase synthesis of single crystalline 3D architectures consisting of epitaxially grown ZnO constituent crystals by position and growth direction controlled growth strategy. The ZnO vertical crystal array was integrated into a piece of polydimethylsiloxane (PDMS) substrate, which was then mechanically detached from the hard substrate to achieve the freestanding ZnO-polymer composite. In addition, the characteristics of transferred ZnO were confirmed by additional structural and photoluminescent measurements. The ZnO vertical crystal array embedded in PDMS was further employed as pressure sensor that exhibited an active response to the external pressure, by piezoelectric effect of ZnO crystal.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.33-37
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• 2019

In this study, the graded thermal properties of composites are obtained by difference in specific gravity of fillers including Cu, h-BN and GO powders in epoxy. Relatively heavy powders such as Cu and h-BN compared to GO mostly at the bottom layer, while light GO powders were dispersed in the top layer in the composites. The thermal conductivity of composites was gradually increased from 0.55 (0.52) W/mK to 2.82 (1.37) W/mK for GO/h-BN (GO/Cu) epoxy composites from surface to bottom. On the contrary, the coefficient of thermal expansion was decreased from 51 ppm/℃ to 23 ppm/℃ and from 57 ppm/℃ to 32 ppm/℃ for GO/Cu and GO/h-BN, respectively. The variation of thermal properties in composites is attributed due to intrinsic material properties of filler including thermal conductivity, morphology and the distribution by the specific weight of fillers. This simple strategy for realizing graded thermal composites by introducing different filler materials would be effective heat transfer at interface of heterostructure with large thermal properties such as inorganic semiconductor/plastic, metal/plastic, and semiconductor/metal.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.11-16
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• 2002

In this study, the dry etching characteristics of $SrBi_2Ta_2O_9$ (SBT) thin films were investigated by using ICP-RIE (inductively coupled plasma-reactive ion etching). The etching damage and degradation were analyzed with XPS (X-ray photoelectron spectroscopy) and C-V (Capacitance-Voltage) measurement. The etching rate increased with increasing the ICP power and the capacitively coupled plasma (CCP) power. The etch rate of 900$\AA$/min was obtained with 700 W of ICP power and 200 W of CCP power. The main problem of dry etching is the degradation of the ferroelectric material. The damage-free etching characteristics were obtained with the $Ar/C1_2/CHF_3$ gas mixture of 20/14/2 when the ICP power and CCP power were biased at 700 W and 200 W, respectively. The experimental results show that the dry etching process with ICP-RIE is applicable to the fabrication of the single transistor type ferroelectric memory device.