1 |
R. Rashidzadeh, “Contactless Test Access Mechanism for TSV Based 3D ICs”, Proc. of VTS, pp. 1-6, April 2013.
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2 |
S. Deutsch and K. Chakrabarty, “Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels”, Proc. of DATE, pp. 1065-1070, Mar. 2013.
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3 |
N. Kandalaft, R. Rashidzadeh, and M. Ahmadi, “Testing 3-D IC Through-Silicon-Vias(TSVs) by Direct Probing,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 4, pp. 538-546, April 2013.
DOI
ScienceOn
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4 |
E. J. Marinissen, D. Y. Lee, J. P. Hayes, C. Sellathamby, B. Moore, S. Slupsky, and L. Pujol, “Contactless testing: Possibility or pipe-dream?”, Proc. of DATE, pp. 676-681, April 2009.
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5 |
J. J. Kim, H. Kim, S. Kim, B. Bae. D. H. Jung, S. Kong, J. Kim, J. Lee, and K. Park, “Non-Contact Wafer-Level TSV Connectivity Test Methodology Using Magnetic Coupling”, Proc. of 3DIC, pp. 1-4, Oct. 2013.
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6 |
K. Dev, G. Woods, and S. Reda, “High-Throughput TSV Testing and Characterization for 3D Integration Using Thermal Mapping”, Proc. of DAC, pp. 1-6, May 2013.
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7 |
H. Kim, J. Cho, J. J. Kim, D. H. Jung, S. Choi, J. Kim, J. Lee, and K. Park, “Eye-diagram simulation and analysis of a high-speed TSV-based channel”, Proc. of 3DIC, pp. 1-7, Oct. 2013.
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8 |
E. J. Marinissen, “Challenges and Emerging Solutions in Testing TSV-Based and 3D-Stacked ICs”, Proc. of DATE, pp. 377-382, July 2012.
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9 |
Internet Article, http://www.samsung.com/global/business/semiconductor/news-events/press-releases/printer?newsId=13602
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10 |
YOLE Development, “3DIC & TSV Technologies: Evolutionof the market drivers and development of the infrastructure”, Presentation Slide, SemiconWest. July 2011.
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11 |
W. W. Shen, “3DIC System Design Impact, Challenge and Solutions”, Presentation Slide, International Symposium on Physical design Mar. 2014.
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12 |
B. Noia, S. Panth, K. Chakrabarty, and S.K. Lim, “Scan Test of Die Logic in 3-D ICs Using TSV Probing”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, accepted for publication.
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13 |
O. Yaglioglu and B. Eldridge, “Direct Connection and Testing of TSV and Microbump Devices using NanoPierce™™ Contactor for 3D-IC Integration”, Proc. of VTS, pp. 96-101, April 2012.
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14 |
D. L. Lewis and H.-H. S. Lee, “A Scan Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors”, Proc. of ITC, pp. 1-8, Oct. 2007.
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15 |
B. Noia and K. Chakrabarty, “Pre-Bond Probing of Through-Silicon Vias in 3D Stacked ICs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 4, pp. 547-558, April 2013.
DOI
ScienceOn
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16 |
C.-Y. Kuo, C.-J. Shih, Y.-C. Lu, J. C.-M. Li, and K. Chakrabarty, “Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits”, IEEE Trans. on VLSI Systems, Vol. 22, No. 3, pp. 667-674, Mar. 2014.
DOI
ScienceOn
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