• Journal of Institute of Control, Robotics and Systems
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• v.15 no.9
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• pp.899-905
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• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as Scratch, Flash, Resin bleed, and Melting. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, Resin bleed and Melting are the most difficult ones to classify accurately. The brightness value and the shape of Resin bleed and Melting defects are so similar that normally it is difficult to classify the Resin bleed and Melting. In this paper, we propose a segmenting method and a set of features for detecting and classifying the Resin bleed and Melting defects.

• Journal of the Korean institute of surface engineering
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• v.55 no.5
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• pp.299-307
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• 2022

Gold plating is used as a coating of connector in printed circuit boards, ceramic integrated circuit packages, semiconductor devices and so on, because the film has excellent electric conductivity, solderability and chemical properties such as durability to acid and other chemicals. In most cases, internal connection between device and package and external terminals for connecting packaging and printed circuit board are electroless Ni-P plating followed by immersion Au plating (ENIG) to ensure connection reliability. The deposition behavior and film properties of electroless Au plating are affected by P content, grain size and mixed impurity components in the electroless Ni-P alloy film used as the underlayer plating. In this study, the correlation between electroless nickel plating used as a underlayer layer and cyanide-free electroless Au plating using thiomalic acid as a complexing agent and aminoethanethiol as a reducing agent was investigated.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.37-44
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• 2000

The corrosion behavior of aluminum pad coated with epoxy molding compound (EMC) was investigated using electrochemical impedance spectroscopy (EIS). The impedance change was evaluated by the absorption of deionized water (DI water) to EMC coating and the interface between EMC and aluminum. During the absorption a decrease in resistance and thus an increase in capacitance of EMC as well as the interface of EMC/Al could be observed. Up to about 170 hours of absorption the EMC was saturated with the water molecules and ions generated from EMC. Subsequently the ionic water was penetrated to the interface and finally the corrosion of aluminum was occurred by the Dl water and ions. From measuring the adhesion strength with the Dl water absorption it was expected that the saturation of water and ions in the interface decreased the adhesion strength. The higher filler content of EMC should be necessary to inhibit the corrosion of aluminum electrode in microelectronic packages.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.7-17
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• 2014

Power electronics modules are semiconductor components that are widely used in airplanes, trains, automobiles, and energy generation and conversion facilities. In particular, insulated gate bipolar transistors(IGBT) have been widely utilized in high power and fast switching applications for power management including power supplies, uninterruptible power systems, and AC/DC converters. In these days, IGBT are the predominant power semiconductors for high current applications in electrical and hybrid vehicles application. In these application environments, the physical conditions are often severe with strong electric currents, high voltage, high temperature, high humidity, and vibrations. Therefore, IGBT module packages involves a number of challenges for the design engineer in terms of reliability. Thermal and thermal-mechanical management are critical for power electronics modules. The failure mechanisms that limit the number of power cycles are caused by the coefficient of thermal expansion mismatch between the materials used in the IGBT modules. All interfaces in the module could be locations for potential failures. Therefore, a proper thermal design where the temperature does not exceed an allowable limit of the devices has been a key factor in developing IGBT modules. In this paper, we discussed the effects of various package materials on heat dissipation and thermal management, as well as recent technology of the new package materials.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.75-79
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• 2013

Demands for semiconductor devices are dramatically increasing, and advancements in fabrication technology are allowing a step-up in the number of devices per unit area. As a result, semiconductor devices require higher heat dissipation, and thus, cooling solutions have become important for guaranteeing their operational reliability. In particular, in chip-in-board packages, in which chips and passives are embedded in the substrates for efficient device layout, heat dissipation is of greater importance. In this study, a thermal model for layers of different materials has been proposed, and then, the heat transfer has been simulated by imposing a set of appropriate boundary conditions. Heat generation can be predicted based on the results, which will be utilized as practical data for actual package design.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.10-14
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• 2019

In this study, we synthesized two $Y_3Al_5O_{12}:Ce^{3+}$ phosphors ($7{\mu}m$-sized and $2{\mu}m$-sized YAG) with different sizes by controlling particles sizes of starting materials of the phosphors for white LED. In the smaller one ($2{\mu}m$-sized YAG), its photoluminescence intensity in the reflective mode was 63 % that of the bigger one ($7{\mu}m$-sized YAG); the quantum efficiencies were 93 % and 70 % for the smaller and the bigger ones. Two kinds of white LED packages with the same color coordinates were fabricated with a blue package (chip size $53{\times}30$) and two phosphors. The luminous flux of the white LED package with the smaller YAG phosphor was 92 % of that with the bigger one, indicating that the quantum efficiency of phosphor dispersed inside LED package was higher than that of the pure powder. It was consistently confirmed by the optical simulation (LightTools 6.3). It is notable according to the optical simulation that the white LED with the smaller phosphor showed 24 % higher luminous efficiency. If the smaller one had the same quantum efficiency as the bigger one (~93 %). Therefore, it can be suggested that the higher luminous efficiency of white LED can be possible by reducing the particle size of the phosphor along with maintaining its similar quantum efficiency.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.1-10
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• 2022

Recently, semiconductor devices have been used in many fields owing to various applications of mobile electronics, wearable and flexible devices and substrates. During the semiconductor chip bonding process, the mismatch of coefficient of therm al expansion (CTE) between the substrate and the solder, and the excessive heat applied to the entire substrate and components affect the performance and reliability of the device. These problems can cause warpage and deterioration of long-term reliability of the electronic packages. In order to improve these issues, many studies on low-melting temperature solders, which is capable of performing a low-temperature process, have been actively conducted. Among the various low-melting temperature solders, such as Sn-Bi and Sn-In, Sn-58Bi solder is attracting attention as a promising low-temperature solder because of its advantages such as high yield strength, moderate mechanical property, and low cost. However, due to the high brittleness of Bi, improvement of the Sn-Bi solder is needed. In this review paper, recent research trends to improve the mechanical properties of Sn-Bi solder by adding trace elements or particles were introduced and compared.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.1-10
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• 2023

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.