Numerical Analysis of Warpage and Stress for 4-layer Stacked FBGA Package
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Kim, Kyoung-Ho
(Graduate School of NID Fusion Technology, Seoul National University of Science and Technology)
Lee, Hyouk (Hanamicron) Jeong, Jin-Wook (Hanamicron) Kim, Ju-Hyung (Hanamicron) Choa, Sung-Hoon (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) |
1 | S. S. Kiyono, K. Yonehara, "Consideration of Mechanical Chip Crack on FBGA Packages", Proc. 2001 Electronic Components and Technology Conference, (2001). |
2 | G. Kelly, C. Lyden, W. Lawton, J. Barrett, A. Saboui, H. Pape and H. Peters, "The Importance of Molding Compound Chemical Shrinkage in the Stress and Warpage Analysis of PQFPs", Proc. 45th Electronic Components and Technology Conference, 977 (1995). |
3 | B. Kiang, J. Wittmershaus, R. Kar and N. Sugai, "Package Warpage Evaluation for Multi-Layer Molded PQFP", Proc. 11th IEEE/CHMT International Electronics on Manufacturing Technology Symposium (IEMT), 89 (1991). |
4 | R. Ingkanisorn and A. Sriyarunya, "RoHS-Compliant Molding Compound Evaluation and Manufacturability For FBGA Packages", Proc. 6th Electronic Packaging Technology Conference (EPTC), 479 (2004). |
5 | L. Yip and A. Hamzehdoost, "Package Warpage Evaluation for High Performance PQFP", Proc. 45th Electronic Components and Technology Conference, 229 (1995). |
6 | K. Irving, Y. Chien, J. Zhang, L. Rector and M. Todd, "Low Warpage Molding Compound Development for Array Packages", Proc. 1st Electronics System integration Technology Conference (ESTC), 2, 1001 (2006). |
7 | C. G. Song and S.-H. Choa, "Numerical Study of Warpage and Stress for the Ultra Thin Package", J. Microelectron. Packag. Soc., 17(4), 49 (2010). 과학기술학회마을 |
8 | J. Zhang, M. O. Bloomfield, J. Lu, R. J. Gutmann and T. S. Cale, "Thermal Stresses in 3D IC Inter-wafer Interconnects", Microelectronic Engin., 82, 534 (2005). DOI |
9 | P. Sun, V. Leung, D. Yang, R. Lou, D. Shi and T. Chung, "Development of a New Package-on-Package (PoP) Structure for Next-Generation Portable Electronics", 2010 Electronic Components and Technology Conference, 1957 (2010). |
10 | T. Jiang and S. Luo, "3D Integration-Present and Future", Proc. 10th Electronics Packaging Technology Conference, 373 (2008). |
11 | S.-H. Hwang, B.-J. Kim, S.-Y. Jung, H.-Y. Lee and Y.-C. Joo, "Thermo-Mechanical Analysis of Though-silicon-via in 3D Packaging", J. Microelectron. Packag. Soc., 17(1), 69 (2010). 과학기술학회마을 |
12 | W. D. van Driel, G. Q. Zhang, J. H. J. Janssen, L. J. Ernst, F. Su, K. S. Chian and S. Yi, "Prediction and Verification of Process-induced Thermal Deformation of Electronic Packages Using Non-linear FEM and 3D Interferometry", Proc. EuroSimE, 362 (2002). |
13 | T. Y. Wu, Y. Tsukad and W. T. Chen, "Materials and Mechanics Issues in Flip-chip Organic Packaging", Proc. 46th Electronic Components and Technology Conference, 524 (1996). |
14 | H. H. Jiun, I. Ahmad, A. Jalar, G. Omar, "Effect of Wafer Thinning Methods Towards Fracture Strength and Topography of Silicon Die", Microelectronics Reliability, 46(5), 836 (2006). DOI |
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