• Journal of Institute of Control, Robotics and Systems
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• v.19 no.12
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• pp.1072-1080
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• 2013

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.7
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• pp.450-454
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• 2018

Because of the rapidly changing environment and high uncertainties, the semiconductor industry is in need of appropriate forecasting technology. In particular, both the cost and time in the test process are increasing because the process becomes complicated and there are more factors to consider. In this paper, we propose a prediction model that predicts a final "good" or "bad" on the basis of preconditioning test data generated in the semiconductor test process. The proposed prediction model solves the classification and regression problems that are often dealt with in the semiconductor process and constructs a reliable prediction model. We also implemented a prediction model through various machine learning algorithms. We compared the performance of the prediction models constructed through each algorithm. Actual data of the semiconductor test process was used for accurate prediction model construction and effective test verification.

• Journal of the Korean Society for Nondestructive Testing
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• v.27 no.3
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• pp.246-254
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• 2007

The scanning laser source (SLS) technique is a promising new laser ultrasonic tool for the detection of small surface-breaking defects. The SLS approach is based on monitoring the changes in laser-generated ultrasound as a laser source is scanned over a defect. Changes in amplitude and frequency content are observed for ultrasound generated by the laser over uniform and defective areas. The SLS technique uses a point or a short line-focused high-power laser beam which is swept across the test specimen surface and passes over surface-breaking or subsurface flaws. The ultrasonic signal that arrives at the Rayleigh wave speed is monitored as the SLS is scanned. It is found that the amplitude and frequency of the measured ultrasonic signal have specific variations when the laser source approaches, passes over and moves behind the defect. In this paper, the setup for SLS experiments with full B-scan capability is described and SLS signatures from small surface-breaking and subsurface flaws are discussed using a point or short line focused laser source.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.1
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• pp.57-62
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• 2002

The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.4
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• pp.1-9
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• 2012

Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined, and numerical experiments are conducted.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.1 no.1
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• pp.17-25
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• 1991

The construction details of VGF apparatus with a DM(direct monitoring) furnace for the growth of low defect crystal and characteristics of GaAs crystal grown by this apparatus are described. The average dislocation densities and EL2 concentration of as-grown undoped GaAs along the different solidified fractions exhibit $4{\times}10^{2}-7{\times}10^{3}cm^{-2}$ and $6{\times}10^{14}-4{\times}10^{15}cm^{-3}$, which are less than those observed for liquid encapsulated Czochralski(LEC) or high-pressure vertical gradient freeze(VGF) crystals. These remarkable reduction of the dislocation densities and EL2 concentrations were explained by the lower temperature gradient ($dT/dx-10^{\circ}/cm$) and slower rates of post - growth cooling ($20^{\circ}C/hr:1240-1000^{\circ}C,\;30^{\circ}C/hr:1000-700^{\circ}C$). Also, The Hall mobilities, carrier concentrations show uniform distribution throughtout 80% of the ingot length.

• Laser Solutions
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• v.16 no.1
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• pp.1-4
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• 2013

The optical properties of III-V compound semiconductor structure was investgated by photoreflectance (PR). The results show two signals at 1.42 and 1.73eV. These are attributed to the bandgap energy of GaAs, AlGaAs, respectively. Also, AlGaAs region showed weak signal. This signal is attributed to carbon or si defect.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.813-815
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• 1992

Accurate Capacitance-Voltage characteristics of Metal-Insulator-Semiconductor (MIS) devices in narrow band-gap semiconductors are presented. The unique band structure of narrow band-gap semiconductors is taken into account such as non-parabolicity and degeneracy. Compensated and partially ionized impurities either in the bulk or the space charge region are also considered. HgCdTe is a defect semiconductor, so this approach is very important for characterization and analysis of MIS devices.