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Simulated Annealing for Reduction of Defect Sensitive Area Through Via Moving  

Lee, Seung Hwan (Department of Computer Science and Industrial Systems Engineering, Yonsei University)
Sohn, So Young (Department of Computer Science and Industrial Systems Engineering, Yonsei University)
Publication Information
Journal of Korean Institute of Industrial Engineers / v.28, no.1, 2002 , pp. 57-62 More about this Journal
Abstract
The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.
Keywords
simulated annealing; layout; defect tolerance; via; yield enhancement;
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