Browse > Article
http://dx.doi.org/10.5302/J.ICROS.2013.13.9037

The GPU-based Parallel Processing Algorithm for Fast Inspection of Semiconductor Wafers  

Park, Youngdae (Dept. of Electronics Engineering, Hoseo University)
Kim, Joon Seek (Dept. of Electronics Engineering, Hoseo University)
Joo, Hyonam (Dept. of Digital Display Engineering, Hoseo University)
Publication Information
Journal of Institute of Control, Robotics and Systems / v.19, no.12, 2013 , pp. 1072-1080 More about this Journal
Abstract
In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.
Keywords
wafer inspection; machine vision; GPU; parallel processing; CUDA;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 T. J. Park, J. M. Woo, and C. H. Kim, "CUDA-based parallel bi-conjugate gradient matrix solver for BioFET simulation," Journal of the Institute of Electronics Engineers of Korea (in Korean), vol. 48, no. 1, pp. 90-100, 2011.   과학기술학회마을
2 G. Vialaneix and T. Boubekeur, "SBL mesh filter: fast separable approximation of bilateral mesh filtering," ACM SIGGRAPH 2011 Talks. ACM, p. 24, 2011.
3 V. Areekul, U. Watchareeruetai, and S. Tantaratana, "Fast separable gabor filter for fingerprint enhancement," Biometric Authentication. Springer Berlin Heidelberg, pp. 403-409, 2004.
4 S. Kurra, N. K. Singh, and P. R. Panda, "The impact of loop unrolling on controller delay in high level synthesis," In IEEE Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6, 2007.
5 J. S. Lee, "Automatic classification algorithm of defects in semiconductor package molding surface inspection using pattern recognition," M. S. Thesis (in Korean), Hoseo University, 2009.
6 R. Bertz and P. Leahy, "Inspection Challenges of Leadless Packages," Proc. SEMOCPN, pp. 418-422, 2002.
7 S. J. Nam and K. S. Hahn, "Implementation of automated defect detection and classification system for semiconductor wafers," Proc. of the 28th KISS Fall Comference (in Korean), vol. 28, no. 2, pp. 334-336, 2001.
8 K. S. Jang and C. H. Jeon "Classification rule-based defect pattern detection of semiconductor wafer map," Proc. of 2005 KIIE Fall Conference (in Korean), pp. 131-139, 2005.
9 S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron, "A performance study of general- purpose applications on graphics processors using CUDA," Journal of Parallel and Distributed Computing, vol. 68, no. 10, pp. 1370-1380, 2008.   DOI   ScienceOn
10 Y. G. Yeom and Y. K. Cho, "High-speed implementation of block ciphers on graphics processing units using CUDA library," Journal of the Korea Institute of Information Security and Cryptology (in Korean), vol. 18, no. 3, pp. 23-31, 2008.
11 M. Moazeni, A. Bui, and M. Sarrafzadeh, "A memory optimization technique for software-managed scratchpad memory if GPUs," 2009 IEEE 7th Symposium on Application Specific Porcessors, pp. 43-49, 2009.
12 NVIDIA, C. U. D. A. NVIDIA CUDA Programming Guide. 2011.