• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.343-343
• /
• 2010

In this paper, Schottky barrier thin-film-transistors (SB-TFTs) with platinum silicide at source/drain region based on glass substrate were fabricated. Poly-silicon on glass substrates was crystallized by excimer laser annealing (ELA) method. The formation of pt-silicide at source/drain region is the most important process for SB-TFTs fabrication. We study the optimal condition of Pt-silicidation on glass substrate. Also, we propose this device as promising structure in the future.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.779-782
• /
• 2003

The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권4호
• /
• pp.381-386
• /
• 2013

A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a $0.13{\mu}m$ CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권2호
• /
• pp.82-87
• /
• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• 대한전자공학회논문지
• /
• 제9권3호
• /
• pp.22-28
• /
• 1972

새로운 전가산기회로를 제안하고 그 동작특성에 관하여 논한다. 회로는 Schottky-Barrier 다이오드 트랜지스터 터낼다이오드로서 구성되며 종래 제안되어 있는 회로의 동작제속도를 개선하고, 트랜지스터 베이스 바이어스전압의 압입 등 회로구성상의 결점을 제거하였다. 정특성곡선을 이용하여 회로구성소자의 최적치를 구하고, 회로동작에 관하여 고찰하였다.

• EDISON SW 활용 경진대회 논문집
• /
• 제3회(2014년)
• /
• pp.450-453
• /
• 2014

쇼트키 장벽 모스펫(Schottky barrier MOSFETs : SB-MOSFETs)은 SB높이(${\Phi}_B$)에 매우 민감하다. 그래서 ${\Phi}_B$를 줄이는 공정 방법에 대한 연구가 활발히 진행 중이다. 이러한 ${\Phi}_B$를 측정할 때, SB-MOSFETs에서가 아닌 SB 다이오드에서 측정이 이뤄지고 있다. 본 논문에서는 ${\Phi}_B$를 SB-MOSFETs에서 측정 할 수 있는 방법을 제안하고 전산모사를 통하여 채널의 길이와 두께, Overlap / Underlap 구조, 온도 등에 대한 의존성을 살펴 보았다. 그 결과 채널의 길이와 두께, Overlap / Underlap 구조에 따른 의존성은 없는 것으로 확인되었다. 하지만 20nm 이하의 채널의 소자에 대해서는 소스/드레인간 터널링 전류로 인해 정확한 ${\Phi}_B$ 측정이 불가능하였다. 그리고 저온에서 측정할 때 정확도가 높아짐을 확인하였다.

• 한국전기전자재료학회논문지
• /
• 제22권9호
• /
• pp.751-755
• /
• 2009

We proposed circular AlGaN/GaN schottky barrier diode, which has no mesa structure near the current path. Proposed device showed low leakage current of 10 nA/mm at -100 V while that of the rectangular device was 34 nA/mm at the same condition. Proposed circular AIGaN/GaN SBD showed high forward current of 88.61 mA at 3,5 V while that of the conventional device was 14.1 mA at the same condition.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.129-130
• /
• 2008

Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.

• 한국전기전자재료학회논문지
• /
• 제22권6호
• /
• pp.462-465
• /
• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Transactions on Electrical and Electronic Materials
• /
• 제16권3호
• /
• pp.151-155
• /
• 2015

We fabricated the Cu Schottky contact on an n-type Ge wafer and investigated the forward bias current-voltage (I-V) characteristics in the temperature range of 100~300 K. The zero bias barrier height and ideality factor were determined based on the thermionic emission (TE) model. The barrier height increased and the ideality factor decreased with increasing temperature. Such temperature dependence of the barrier height and the ideality factor was associated with spatially inhomogeneous Schottky barriers. A notable deviation from the theoretical Richardson constant (140.0 Acm^-2K^-2 for n-Ge) on the conventional Richardson plot was alleviated by using the modified Richardson plot, which yielded the Richardson constant of 392.5 Acm^-2K^-2. Finally, we applied the theory of space-charge-limitedcurrent (SCLC) transport to the high forward bias region to find the density of localized defect states (N_t), which was determined to be 1.46 × 10¹² eV^-1cm^-3.