• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.

• 한국컴퓨터정보학회논문지
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• 제13권4호
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• pp.87-95
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• 2008

경계면 스캔 구조는 시험대상회로의 출력 값들을 캡쳐하여 스캔경로를 이용하여 TDO로 직렬출력하여 출력 값을 관찰할 수 있는 시험구조이며, Sample/preload명령어를 이용하여 시험대상회로의 특정한 한 순간의 출력만을 캡쳐하여 직렬출력하여 분석할 수 있다. 본 논문에서는 4비트 비동기 카운터회로를 시험대상회로로 선정하고, 정상동작중인 카운터의 특정 출력을 지정하여 특정한 순간의 정적인 출력이 아닌, 연속적인 동적인 출력 값들을 다른 출력결과의 영향 없이 지속적으로 TDO로 출력하여 관찰할 수 있는 선택 가능한 관측점을 가진 시험구조와 시험절차를 개발하였다. 본 논문에서 제안하는 선택 가능한 관측점을 가진 시험구조는 표준에서 정한 시험동작을 정상적으로 수행하며, 관측점의 설정을 위한 명령어가 추가되었다. 4비트 카운터회로에 제안된 선택 가능한 관측점 시험구조를 적용 설계하고, 관측점 설정 명령어를 사용한 시험절차를 Altera의 Max 10.0을 이용한 시뮬레이션을 통해 동작의 정확성을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.124-130
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• 2014

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.

• 전자공학회논문지C
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• 제36C권2호
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• pp.14-25
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• 1999

인쇄 회로 보드 수준의 테스팅을 위해 제안된 IEEE 표준 1149.1은 보드상의 테스트 지점에 대한 제어용이도와 관측용이도를 향상시켜 보드의 테스트를 용이하게 해준다. 그러나, 경계 주사 환경에서는 테스트 입력과 테스트 결과에 따른 데이터가 하나의 주사 연결에 의해서 직렬로 이동된다. 이는 테스트 적용시간을 증가시키고 따라서 테스트에 드는 비용을 증가시킨다. 테스트에 소모되는 시간을 줄이기 위해 병렬로 다중주사 경로를 구성하는 방법이 제안되었다. 하지만 이는 여분의 입출력 핀과 내선을 필요로 한다. 더구나 IEEE 표준 1149.1은 주사 경로 상에 있는 IC들의 병렬 동작을 지원하지 않기 때문에 표준에 맞게 설계하기가 어렵다. 본 논문에서는 하나의 테스트 버스로 두 개의 주사 경로를 동시에 제안하는 다중 주사 경로 접근 알고리즘에 기초하여 적은 면적 오버헤드를 가지고 빠른 시간 내에 보드를 테스트할 수 있는 새로운 보드수준의 내장된 자체 테스트 구조를 구현하였다. 제안된 내장된 자체 테스트 구조는 두 개의 주사 경로에 대한 테스트 입력과 테스트 결과를 이동시킬 수 있으므로 테스트에 소모되는 시간을 줄일 수 있고 또한 테스트 입력의 생성과 테스트 결과의 분석에 소모되는 비용을 줄일 수 있다.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.201-206
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• 2007

본 논문에서는 NoC(Network-on Chip) 구조로 구현된 core-based 시스템에 대한 효율적인 저전력 테스트 방법을 제안한다 NoC의 라우터 채널로 전송되는 테스트 데이터의 전력소모를 줄이기 위해서 스캔 벡터들을 채널 폭만큼의 길이를 갖는 flit으로 분할하고 nit간 천이율(switching rate)이 최소화 되도록 don't care 입력을 할당하였다. ISCAS 89 벤치마크에 대하여 실험을 한 결과, 제안된 방법은 약 35%의 전력 감소를 나타내었다.

• 대한전기학회논문지:전력기술부문A
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• 제48권9호
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.221-228
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• 2007

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

• 대한디지털의료영상학회논문지
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• 제17권1호
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• pp.49-56
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• 2015

Temporal bone CT scan side skull fracture. In addition to the confirmation of the ossicles, such as fractures and dislocations, temporomandibular facial fractures, deformities surgery helps to establish a science plan. Cochlear implant surgery has been performed in the state before and after identifying purposes. Test methods are being implemented by the Conventional direct axial and Direct coronal scan, the basic method of Temporal bone CT. Helical scan is a fast Volumetric data obtained compared with the Conventional scan, the patient reduced the dose, and there are some advantages, such as reduced Beam hardening streak artifacts caused by dental fillings. This study is a comparative analysis by dose reduction for patients with a dose according to the conventional scan method and then effective from 2015 by helical scan method performed in 2014 through the retrospective survey, which was then optimized for the purpose of inspection.

• 대한전자공학회논문지SD
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• 제40권7호
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• pp.474-480
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• 2003

We designed and tested a new scan driver output stage. Compared to conventional CMOS structured scan driver IC′s, the new NMOSFET-only scan driver circuit can reduce the chip area and therefore, the chip cost considerably. We confirmed the circuit operation with open drain power NMOSFET IC′s by driving 2"PDP test panel. We defined critical device parameters and their optimization methods lot the best circuit performance.

• 한국임상수의학회지
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• 제34권5호
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• pp.330-334
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• 2017

The aim of this study was to establish an injection protocol of a test bolus and a main bolus of contrast material for computed tomographic pulmonary angiography (CTPA) for visualizing optimal pulmonary arteries in normal beagle dogs. CTPA using a test bolus method from either protocol A or B were performed in each of four normal beagle dogs. In protocol A, CTPA was conducted with a scan duration for around 8 s, setting the contrast enhancement peak of the pulmonary trunk in the middle of the scan duration. The arrival time to the contrast enhancement peak was predicted from a previous dynamic scan using a test bolus (150 mg iodine/kg) injected with the same injection duration using for a main bolus (450 mg iodine/kg). In protocol B, CTPA was started at the predicted appearance time of contrast material in the pulmonary trunk based on a previous dynamic scan using a test bolus injected with the same injection rate as a main bolus. CTPA using protocol A showed the optimal opacification of the pulmonary artery with pulmonary venous contamination. Proper CTPA images in the absence of venous contamination were obtained in protocol B. CTPA with a scan duration for 8 s should be started at the appearance time of contrast enhancement in the pulmonary trunk, which can be identified exactly when a test bolus is injected at the same injection rate used for the main bolus.