[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2014.14.1.124

A Scan-Based On-Line Aging Monitoring Scheme

Yi, Hyunbean (Dept. of Computer Engineering/Graduate School of Information & Communications, Hanbat National University)
Yoneda, Tomokazu (Graduate School of Information Science, Nara Institute of Science and Technology (NAIST))
Inoue, Michiko (Graduate School of Information Science, Nara Institute of Science and Technology (NAIST))

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.14, no.1, 2014 , pp. 124-130 More about this Journal

Abstract

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.

Keywords

Aging monitor; scan test; delay test; online test; system-on-chip (SoC);

Citations & Related Records

Reference

1	International Technology Roadmap for Semiconductors, 2009 Edition.
2	W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, and Y. Cao, "Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS technology," IEEE Trans. On Device and Material Reliability, VOL. 7, NO. 4, pp. 509-517, Dec. 2007. DOI
3	T. W. Chen, K. Kim, Y. M. Kim, and S. Mitra, "Gate-Oxide Early Failure Prediction," Proc. IEEE VLSI Test Symp., pp. 111-118, 2008.
4	M. Noda, S. Kajihara, Y. Sato, and Y. Miura, "On Estimation of NBTI-Induced Delay Degradation," IEEE European Test Symp., pp. 107-111, May 2010.
5	Y. Li, S. Makar, and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns," Proc. Design Automation and Test in Europe, pp. 885-890, 2008.
6	H. Yi, T. Yoneda, M. Inoue, Y. Sato, S. Kajihara, and H. Fujiwara, "A Failure Prediction Strategy for Transistor Aging," IEEE Trans. on VLSI Systems, pp. 1-9, Oct. 2011.
7	Y. Sato, S. Kajihara, Y. Miura, T. Yoneda, S. Ohtake, M. Inoue, and H. Fujiwara, "A Circuit Failure Prediction Mechnism (DART) for High Field Reliability," Proc. Int'l Conf. on ASIC, pp. 581-584, Oct. 2009.
8	H. Inoue, Y. Li, and S. Mitra, "VAST: Virtualization-Assisted Concurrent Autonomous Self-Test," Proc. Int'l Test Conf., pp. 1-10, 2008.
9	Y. Li, O. Mutlu, and S. Mitra, "Operating System Scheduling for Efficient Online Self-Test in Robust Systems," Int'l Conf. on Computer-Aided Design, pp. 201-208, 2009.
10	T. Sato and Y. Kunitake, "A Simple Flip-Flop Circuit for Typical-Case Designs for DFM," 8th International Symposium on Quality Electronic Design, pp. 539-544, 2007.
11	M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra, "Circuit Failure Predition and Its Application to Transistor Aging," Proc. IEEE VLSI Test Symp., pp. 277-284, 2007.
12	T. Nakura, K. Nose, and M. Mizuno, "Fine Grain redundant Logic Using Defect-Prediction Flip- Flops," IEEE Int'l Solid-State Circuits Conf., pp. 402-403, 2007.
13	J. Park and J. A. Abraham, "An Aging-Aware Flip- Flop Design Based on Accurate, Run-Time Failure Prediction," Proc. IEEE VLSI Test Symp., pp. 294- 299, 2012
14	O. Khan and S. Kundu, "A Self-Adaptive System Architecture to Address Transistor Aging," Proc. Design Automation and Test in Europe, pp. 81-86, 2009.
15	J. K. Eitrheim, "Adjustable Duty Cycle Clock Generator," U. S. Patent, PN: 5,638,016, June 1997.
16	M. Karlsson, M. Vesterbacka, and W. Kulesza, "A Non-Overlapping Two-Phase Clock Generator with Adjustable Duty Cycle," Proc. Linköping Electonic Conf., pp. 1-4, Nov. 2003.
17	D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," 36th International Symposium on Microarchitecture, pp. 7-18, 2003.