JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A New Scan Chain Fault Simulation for Scan Chain Diagnosis

  • Chun, Sung-Hoon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Tae-Jin (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Park, Eun-Sei (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • Published : 2007.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

Keywords

References

  1. J. Schafer, F. Policastri and R. Mcnulty, 'Partner SRLs for Improved Shift Register Diagnostics,' Proceedings of VLSI Test Symposium, pp. 198-201, 1992
  2. S. Edirisooriya and G. Edirisooriya, 'Diagnosis of Scan Path Failures,' Proceedings of VLSI Test Symposium, pp. 250-255. 1995
  3. S. Narayanan and A. Das, 'An Efficient Scheme to Diagnose Scan Chains,' Proceedings of International Test Conference, pp. 704-713,1997
  4. Y. Wu, 'Diagnosis of Scan Chain Failures,' Proceedings ofInternational Test Conference, pp. 268-277, 2001
  5. S. Kundu, 'On Diagnosis of Faults in a ScanChain,' Proceedings of VLSI Test Symposium, pp. 303-308, 1993
  6. K. Stanley, 'High Accuracy Flush and Scan Software Diagnostic,' Proceedings of IEEE Workshop on Yield Optimization & Test, 2000
  7. R. Guo and S. Venkataraman, 'An algorithmic technique for diagnosis of faulty scan chains,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, pp. 1861-1868, 2006
  8. Y. -L. Kao, W.-S. Chuang and J. -M. Li, 'Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis,' Proceedings of International Test Conference, pp. , 2006
  9. Y. Huang, W. T. Cheng, C. J. Hsieh, H. Y. Tseng, A. Huang and Y. T. Hung, 'Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults,' Proceedings of Asian Test Symposium, pp. 44-49,2003
  10. Y. Huang, W. T. Cheng, C. J. Hsieh, H. Y. Tseng, A. Huang and Y. T. Hung, 'Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis,' Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 1072-1077,2004
  11. Y. Huang, W. T. Cheng and G. Crowell, 'Using Fault Model Relaxation to Diagnose Real Scan Chain Defects,' Proceedings of Asia and South Pacific Design Automation Conference, pp. 11761179,2005
  12. Mentor Graphics, 'LEISTArchitect Reference Manual,' Version 8.9_1