• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Journal of the Korean Magnetics Society
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• v.15 no.6
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• pp.332-335
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• 2005

Output voltage of the flux-meter has always drift due to the input bias current of non-ideal operational amplifier. In this study we have employed a digital sample and hold amplifier which has no voltage drop to compensate drift of the flux-meter automatically. The drift of the developed flux-meter was smaller than $5{\times}10^{-8}\;Wb/s$ for the integration time constant of $RC=10^{-3}$ s.

• Journal of Magnetics
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• v.8 no.4
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• pp.160-163
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• 2003

In magnetic flux measurement, output voltage drift of electronic integrator is an essential problem. In this work, we have developed a new kind of Miller type integrator using a sample and hold amplifier. Input bias current was measured and this value was hold in the sample and hold amplifier, after that input bias current of Miller integrator was compensated automatically using the value which holds in the sample and hold amplifier. Developed flux-meter shows the drift of flux-meter are smaller than 10$^{-5}$ Wb/min in full scale of 10$^{-2}$, and we could also measure multi-channel magnetic flux simultaneously.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.27-33
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• 2016

This paper proposes a Low Noise Amplifier (LNA) with chopper stabilization technique with a sample-hold circuit. Chopper stabilization technique is effective in terms of reducing low frequency offset and flicker noise. Conventional chopper amplifier has a disadvantage in area because of using Low Pass Filter (LPF) for remove chopping spike. The proposed chopper amplifier employed sample and hold technique to decrease chopping spike instead of LPF that improves 36% in voltage damping and 11% in area.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.280-285
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• 2004

In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-$\mu\textrm{m} $ CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.825-831
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• 2016

In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.