• Journal of Power Electronics
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• 제16권1호
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• Journal of Power Electronics
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• 제14권5호
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• pp.1057-1068
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• 2014

Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-used for grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of a SRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.

• 조명전기설비학회논문지
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• 제28권11호
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• 전력전자학회논문지
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• 제14권2호
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• pp.134-141
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• 2009

전원사고로 인하여 야기되는 전원급변상황에서 위상각의 새로운 PLL 방법은 추종속도를 개선시키기 위하여 제안되었다. 일반적으로 측정된 전원이 이상적이지 않고 고조파가 포함되어 있으며 센서의 노이즈 때문에 동기좌표계 PLL의 피드백 루프에는 LPF를 사용하고 있다. 그러므로 과도상태의 빠른 동특성을 얻기 위해서 LPF를 고려한 PLL시스템의 모델링을 제안하였다. 또한 전원의 급변 시에 빠른 위상각 검출을 위한 방법으로 자동으로 제어기 대역폭과 LPF의 차단주파수를 변동시키는 가변 파라미터 PLL방법을 제안하였다. 이를 시뮬레이션과 실험을 통해 검증하여 유효성을 보이고자 한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 추계학술대회 논문집
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• pp.71-73
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• 2008

급변하는 전압 변동 상황에서 전력 제어를 수행하기 위해서 기존의 동기좌표 위상각 검출 제어기의 특성을 보완할 수 있는 방법을 제시하였다. 실질적인 SRF (Synchronous Reference Frame) - PLL(Phase Locked Loop) 시스템에서 계통 전압은 이상적이지 않고 센서 노이즈 등의 저감을 위하여 측정된 전압에 LPF(Low Pass Filter)를 사용하고 있는데 이러한 LPF의 특성을 고려하여 위상각 제어기의 PI게인을 설정하는 방법을 제시하였으며 가변 게인과 LPF 차단주파수 변동방식을 이용하여 전원 전압 사고의 종류에 따라 위상과 전압이 급변하는 경우에 대하여 시뮬레이션과 실험을 통해 제한된 방법으로 동특성이 개선되고 원하는 응답속도로 설계가 가능함을 보였다.

• 조명전기설비학회논문지
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• 제29권10호
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• pp.73-82
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• 2015

This paper proposes an ripple reduction algorithm and analyzes the effects of offset and scale errors generated by voltage sensor while measuring grid voltage in grid-tied single-phase inverters. Generally, the grid-connected inverter needs to detect the phase angle information by measuring grid voltage for synchronization, so that the single-phase inverter can be accurately driven based on estimated phase angle information. However, offset and scale errors are inevitably generated owing to the non-linear characteristics of voltage sensor and these errors affect that the phase angle includes 1st harmonic component under using SRF-PLL(Synchronous Reference Frame - Phase Locked Loop) system for detecting grid phase angle. Also, the performance of the overall system is degraded from the distorted phase angle including the specific harmonic component. As a result, in this paper, offset and scale error due to the voltage sensor in single-phase grid connected inverter under SRF-PLL is analyzed in detail and proportional resonant controller is used to reduce the ripples caused by the offset error. Especially, the integrator output of PI(Proportional Integral) controller in SRF-PLL is selected as an input signal of the proportional resonant controller. Simulation and experiment are performed to verify the effectiveness of the proposed algorithm.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.281-282
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• 2014

본 논문은 FPGA 기반의 DSC-PLL(Delayed Signal Cancellation - Phase Locked Loop)을 설계하고, 왜곡된 3상전압 조건에서 위상추종결과를 비교실험 하였다. FPGA 구현 알고리즘은 Matlab/Simulink와 연동된 System Generator를 이용하여 DSC-PLL 모델을 설계하고, Verilog HDL 코드로 변환 하였다. 불평형 및 고조파를 포함한 왜곡된 3상 전압 조건에서 FPGA에 구현된 DSC-PLL과 SRF-PLL (Synchronous Reference Frame - Phase Locked Loop)의 d-q축 고조파 감쇠특성 및 위상추종능력을 실험을 통해 비교하였다. DSC-PLL은 약 5.44ms 이내에 d-q축 고조파 성분을 제거함으로써 정상분 기본파 전압의 위상을 빠르게 추종하는 것을 검증하였다.

• Journal of Power Electronics
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• 제17권3호
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• pp.704-715
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• 2017

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.

• Journal of Power Electronics
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• 제11권3호
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• pp.369-374
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• 2011

Usually, a LPF (low pass filter) is used in the feedback loop of a SRF (synchronous reference frame) - PLL (phase locked loop) system because the measured grid voltage contains harmonic distortions and sensor noises. In this paper, it is shown that the cut-off frequency of the LPF should be designed to suppress the harmonic ripples contained in the measured voltage. Also, a new design method for the loop gain of the PI-type controller in the SRF-PLL is proposed with consideration of the dynamics of the LPF. As a result, a better transient response can be obtained with the proposed design method. The LPF frequency and the PI controller gain are designed in coordination according to the steady state and dynamic performance requirements. Furthermore, in the proposed method, the controller gain and the LPF cut-off frequency are changed from their normal value to a transient value when a voltage disturbance is detected. This paper shows the feasibility and usefulness of the proposed methods through the computer simulations and experimental results.

• 전력전자학회논문지
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• 제23권4호
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.