Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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A Hybrid Filtering Stage Based Quasi-type-1 PLL under Distorted Grid Conditions

  • Li, Yunlu (School of Information Science and Engineering, Northeastern University) ;
  • Wang, Dazhi (School of Information Science and Engineering, Northeastern University) ;
  • Han, Wei (School of Physics and Electronics Information, Inner Mongolia University for the Nationalities) ;
  • Sun, Zhenao (School of Information Science and Engineering, Northeastern University) ;
  • Yuan, Tianqing (School of Information Science and Engineering, Northeastern University)
  • Received : 2016.11.29
  • Accepted : 2017.02.13
  • Published : 2017.05.20
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Abstract

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.

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References

  1. L.-Y. Yang, C.-L. Wang, J.-H. Liu, and C.-X. Jia, "A novel phase locked loop for grid connected converters under non-ideal grid conditions," Journal of Power Electronics, Vol. 15, No. 1, pp. 216-226, Jan. 2015. https://doi.org/10.6113/JPE.2015.15.1.216
  2. Z. Luo, M. Su, Y. Sun, Z. Liu, and M. Dong, "First-order generalized integrator based frequency locked loop and synchronization for three-phase grid-connected converters under adverse grid conditions," Journal of Power Electronics, Vol. 16, No. 5, pp. 1939-1949, Sep. 2016. https://doi.org/10.6113/JPE.2016.16.5.1939
  3. Y. Li, D. Wang, W. Han, S. Tan, and X. Guo, "Performance improvement of quasi-type-1 pll by using a complex notch filter," IEEE Access, Vol. 4, pp. 6272-6282, Oct. 2016. https://doi.org/10.1109/ACCESS.2016.2614008
  4. H.-J. Choi, S.-H. Song, S.-G. Jeong, J.-Y. Choi, and I. Choy, "Enhanced dynamic performance during voltage disturbance," Journal of Power Electronics, Vol. 11, No. 3, pp. 369-374, May 2011. https://doi.org/10.6113/JPE.2011.11.3.369
  5. S. Golestan, M. Monfared, F. D. Freijedo, and J. M. Guerrero, "Design and tuning of modified power-based pll for single phase grid-connected power conditioning systems," IEEE Trans. Power Electron., Vol. 27, No. 8, pp. 3639-3650, Aug. 2012. https://doi.org/10.1109/TPEL.2012.2183894
  6. P. Rodriguez, R. Teodorescu, I. Candela, A. V. Timbus, M. Liserre, and F. Blaabjerg, "New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions," in Proc. IEEE Power Electron. Spec. Conf., pp. 1-7, 2006.
  7. P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and D. Boroyevich, "Decoupled double synchronous reference frame PLL for power converters control," IEEE Trans. Power Electron., Vol. 22, No. 2, pp. 584-592, Mar. 2007. https://doi.org/10.1109/TPEL.2006.890000
  8. P. Rodriguez, A. Luna, I. Etxeberria, J. R. Hermoso, and R. Teodorescu, "Multiple second order generalized integrators for harmonic synchronization of power converters," in Proc. IEEE Energy Convers. Congr. Expo., pp. 2239-2246, 2009.
  9. X. Guo, W. Wu, and Z. Chen, "Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks," IEEE Trans. Ind. Electron., Vol. 58, No. 4, pp. 1194-1204, Apr. 2011. https://doi.org/10.1109/TIE.2010.2041738
  10. S. Golestan, M. Monfared, and F. D. Freijedo, and J. M. Guerrero, "Performance improvement of a prefiltered synchronous-reference-frame pll by using a PID-type loop filter," IEEE Trans. Power Electron., Vol. 61, No. 7, pp. 3469-3479, July. 2014.
  11. S. Golestan, M. Monfared, and F. D. Freijedo, "Design-oriented study of advanced synchronous reference frame phase-locked loops," IEEE Trans. Power Electron., Vol. 28, No. 2, pp. 765-778, Feb. 2013. https://doi.org/10.1109/TPEL.2012.2204276
  12. S. Golestan, J. M. Guerrero, A. Vidal, A. G. Yepes and J. Doval-Gandoy, "PLL with MAF-based prefiltering stage: small-signal modeling and performance enhancement," IEEE Trans. Power Electron., Vol. 31, No. 6, pp. 4013-4019, June. 2016. https://doi.org/10.1109/TPEL.2015.2508882
  13. S. Golestan, M. Ramezani, J. M. Guerrero, F. D. Freijedo, M. Monfared, "Moving average filter based phase-locked loop: performance analysis and design guidelines," IEEE Trans. Power Electron., Vol. 29, No. 6, pp. 2750-2763, June. 2014. https://doi.org/10.1109/TPEL.2013.2273461
  14. S. Golestan, J. M. Guerrero, A. M. Abusorrah, "MAF-PLL with phase-lead compensator," IEEE Trans. Ind. Electron., Vol. 62, No. 6, pp. 3691-3695, June. 2015. https://doi.org/10.1109/TIE.2014.2385658
  15. Jinyu Wang, Jun Liang, Feng Gao, Li Zhang, and Zhoudi Wang, "A method to improve the dynamic performance of moving average filter-based pll," IEEE Trans. Power Electron., Vol. 30, No. 10, pp. 5978-5990, Oct. 2015. https://doi.org/10.1109/TPEL.2014.2381673
  16. L. Hadjidemetriou, E. Kyriakides, F. Blaabjerg, "An adaptive tuning mechanism for phase-locked loop algorithm for faster time performance of interconnected renewable energy sources," IEEE Trans. Ind. Appl., Vol. 51, No. 2, pp. 1792-1804, Apr. 2015. https://doi.org/10.1109/TIA.2014.2345880
  17. L. Hadjidemetriou, E. Kyriakides, F. Blaabjerg, "A robust synchronization to enhance the power quality of renewable energy systems," IEEE Trans. Ind. Electron., Vol. 62, No. 8, pp. 4858-4868, Aug. 2015. https://doi.org/10.1109/TIE.2015.2397871
  18. S. Golestan, F. D. Freijedo, A. Vidal, J. M. Guerrero, and J. Doval Gandoy, "A quasi-type-1 phase-locked loop structure," IEEE Trans. Power Electron., Vol. 29, No. 12, pp. 6264-6270, Dec. 2014. https://doi.org/10.1109/TPEL.2014.2329917
  19. S. Golestan, J. M. Guerrero, A. M. Abusorrah, Y. Al-Turki, "Hybrid synchronous/stationary reference-frame-filtering based pll," IEEE Trans. Ind. Electron., Vol. 62, No. 8, pp. 5018-5022, Aug. 2015. https://doi.org/10.1109/TIE.2015.2393835
  20. S. Golestan, J. M. Guerrero, Ana Vidal, A. G. Yepes, J. Doval-Gandoy, F. D. Freijedo, "Small-signal modeling, stability analysis and design optimization of single-phase delay-based plls," IEEE Trans. Power Electron., Vol. 31, No. 5, pp. 3517-3527, May. 2016. https://doi.org/10.1109/TPEL.2015.2462082
  21. S.Golestan, M. Ramezani, J. M. Guerrero, M. Monfared, "dq-frame cascaded delayed signal cancellation-based pll: analysis, design, and comparison with moving average filter-based pll," IEEE Trans. Power Electron., Vol. 30, No. 3, pp. 1618-1632, Mar. 2015. https://doi.org/10.1109/TPEL.2014.2315872
  22. Y. F. Wang and Y. W. Li, "Three-phase cascaded delay signal cancellation pll for fast selective harmonic detection," IEEE Trans. Ind. Electron., Vol. 60, No. 4, pp. 1452-1463, Apr. 2013. https://doi.org/10.1109/TIE.2011.2162715
  23. Y. F. Wang and Y. W. Li, "Grid synchronization pll based on cascaded delay signal cancellation," IEEE Trans. Power Electron., Vol. 26, No. 7, pp. 1987-1997, Jul. 2011. https://doi.org/10.1109/TPEL.2010.2099669
  24. S. Golestan, A. Vidal, A. G. Yepes, J. M. Guerrero, J. C. Vasquez and J. Doval-Gandoy, "A true open-loop synchronization technique," IEEE Trans. Ind. Inform., Vol. 12, No. 3, pp. 1093-1103, Jun. 2016 https://doi.org/10.1109/TII.2016.2550017
  25. Qicheng Huang and K. Rajashekara, "An improved delayed signal cancellation pll for fast grid synchronization under distorted and unbalanced grid condition," in 2016 IEEE Industry Applications Society Annual Meeting, pp. 1-7, 2016.
  26. S. Golestan, F. D. Freijedo, A. Vidal, A. G. Yepes, J. M. Guerrero, J. Doval-Gandoy, "An efficient implementation of generalized delayed signal cancellation pll," IEEE Trans. Power Electron., Vol. 31, No. 2, pp. 1085-1094, Feb. 2016. https://doi.org/10.1109/TPEL.2015.2420656
  27. S. Golestan, M. Monfared, and F. D. Freijedo, "Design-oriented study of advanced synchronous reference frame phase-locked loops," IEEE Trans. Power Electron., Vol. 28, No. 2, pp. 765-778, Feb. 2013. https://doi.org/10.1109/TPEL.2012.2204276
  28. F. Gonzalez-Espin, E. Figueres, and G. Garcera, "An adaptive synchronous-reference-frame phase-locked loop for power quality improvement in a polluted utility grid," IEEE Trans. Ind. Electron., Vol. 59, No. 6, pp. 2718-2731, Jun. 2012. https://doi.org/10.1109/TIE.2011.2166236
  29. M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, "A new single-phase PLL structure based on second order generalized integrator," in Proc. 37th PESC, pp. 1-6, 2006.
  30. M. Tsili and S. Papathanassiou, "A review of grid code technical requirements for wind farms," IET Renew. Power Gener., Vol. 3, No. 3, pp. 308-332, Sep. 2009. https://doi.org/10.1049/iet-rpg.2008.0070
  31. Alvaro Luna, Joan Rocabert, J. Ignacio Candela, Juan Romon Hermoso, Remus Teodorescu, Frede Blaabjerg, Pedro Rodriguez, "Grid voltage synchronization for distributed generation systems under grid faults conditions," IEEE Trans. Ind. Appl., Vol. 51, No. 4, pp. 3414-3425, Jul. 2015. https://doi.org/10.1109/TIA.2015.2391436
  32. e-on, "Grid code-High and extra high voltage," Bayreuth, Germany. Apr. 2006. [Online]. Available: https://www.bayernwerk.de/cps/rde/xbcr/bayernwerk/NAR_englisch.pdf.
  33. PO-12.3 Requisitos de Respuesta Frente a Huecos de Tension de las Instalaciones Eolicas, Comision Nacional de Energia, Madrid, Spain, Oct. 2006.
  34. IEEE Standard for Interconnecting Distributed Resources With Electric Power Systems, IEEE Std. 1547-2003, 2003.
  35. The Grid Code: Revision 31, National Grid Electricity Transmission, Warwick, U.K., Oct. 2008, no. 3. [Online]. Available: http://www2.nationalgrid.com/uk/industryinformation/electricity-codes/grid-code/the-grid-code/
  36. Z. Xin, X. Wang, Z. Qin, M. Lu, P. C. Loh, and F. Blaabjerg, "An improved second-order generalized integrator based quadrature signal generator," IEEE Trans. Power Electron., Vol. 31, No. 12, pp. 8068-8073, Dec. 2016. https://doi.org/10.1109/TPEL.2016.2576644
  37. S. Golestan, J. M. Guerrero, and G. B. Gharehpetian, "Five approaches to deal with problem of dc offset in phase-locked loop algorithm: design considerations and performance evaluations," IEEE Trans. Power Electron., Vol. 31, No. 1, pp. 648-661, Jan. 2016. https://doi.org/10.1109/TPEL.2015.2408113

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