• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.435-437
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• 1994

Cramped resonant DC link inverter is analyzed by widely available software such as SPICE. In this paper, the model of ACRDCL which is based on converter switch function rather than actual circuit configuration is used. Power circuit is modeled by functional transfer function and the controller is based on the macro-model. Computer memory and runtime are based reduced compared to micro-model. Overall performance including control strategy and harmonic characteristics in the steady state can be analyzed easily.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.12
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• pp.6046-6051
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• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor for secure communication applications. Proposed chaotic circuit consist of passive devices such as L and C, a MOS based variable resistor and a transcondcutor based Chua's diode. From SPICE simulation results, the proposed circuit showed variable chaotic dynamics through time waveforms, frequency analysis and phase plots.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.9
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• pp.686-691
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• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor. Proposed chaotic circuit consist of L, C, R and transcondcutor based Chua's diode. We performed SPICE simulation for chaotic dynamics such as time seriesform, frequency analysis and phase plane of the circuit. Chaotic dynamics of the circuit was analysed according to MOS size variation of the operational transconductance amplifier. Also, we performed SPICE circuit analysis for temperature dependance of the circuit. SPICE results showed that chaotic dynamics of the circuit varied according to the temperature variation and chaotic signals were generated in specific temperature conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.341-346
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• 2013

Threshold voltage shift caused by trapping and release of charge carriers in a thin-film transistor (TFT) is implemented in AIM-SPICE tool. Turning on and off voltages are alternatively applied to a TFT to extract charge trapping and releasing process. Each process is divided into sequentially ordered processes, which are numerically modeled and implemented in a computer language. The results show a good agreement with the experimental data, which are modeled. Since the proposed method is independent of TFT's behavior models implemented in SPICE tools, it can be easily added to them.

• Journal of Sensor Science and Technology
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• v.21 no.5
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• pp.389-393
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• 2012

A chaotic oscillator with light controllability was designed. The proposed chaotic oscillator consists of a photo sensor, two phase clock driven MOS switches, nonlinear function blocks for chaotic signal generation. SPICE circuit analysis using a 0.35 um CMOS process parameters was performed for its chaotic dynamics. And we confirmed that chaotic behaviors of the circuit can be controlled according to light intensity. By SPICE simulation, chaotic dynamics by time waveforms, frequency analysis was analyzed. SPICE results showed that proposed circuit can make various light-controlled chaotic signals.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.715-717
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• 1993

Resonant Inverter is analyzed by means of widely available software such a SPICE. In this paper, macro-model of RDCLI is used which is based on converter switch function rather than actual circuit configuration. Computer memory and nm time are greatly reduced compared to micro-model by using macro-model. System overall performance including control strategy and harmonic characteristics can be analyzed easily. This method is suited for stead state analysis and transition analysis at system level.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.131-139
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• 1989

This paper proposes Domino CMOS NOR-NOR Array Logic design method which has the same as characteristic of CMOS and Domino CMOS in Array Logic like PLA, good operation feature, high desity, easy test generation. This testable design method can detect all of faults in the circuit using simple additional circuit and solve the parasitic capacitance problem by improving the pull-down characteristics. A Test generation algorithm and test procedure using concept of PLA product term and personality matrix are proposed, and it was implemented in PASCAL language. This design method is verified by SPICE and P-SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.54-61
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• 1999

We suggested a macro medel for MOS transistors, which incorporates the distributed substrate resistance by using a method which utilizes external diodes on SPICE MOS model. By fitting the simulated s-parameters to the measures ones, we obtained a model set for the W=200TEX>$\mu\textrm{m}$ and L=0.8TEX>$\mu\textrm{m}$ NMOS transistor, and also analyzed the effects of distributed substrate resistance in the RF range. By comparing the physical parameters calculated from simulated s-parameters such as ac resistances and capacitances with the measured ones, we confirmed the validity of the simulation results. For the frequencies below 10GHz, it seems appropriated to use a simple macro model which utilizes the existing SPICE MOS model with junction diodes, after including one lumped resistor each for gate and substrate nodes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.124-127
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• 2002

A CMOS voltage regulation circuit for use at low-voltage is proposed. Circuits for a positive and for a negative current regulation are presented and are designed with commercial CMOS technology. The voltage regulation that is stable over ambient temperature variations is an important component of most data acquisition systems. These results are verified by the H-SPICE simulation $0.8{\mu}m$ parameter. As the result, the temperature dependency of output voltage is $0.57mV/^{\circ}C$ and the power dissipation is 1.8 mV on 5V supply voltage.