• Title/Summary/Keyword: SONOS NOR array

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Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

  • An, Ho-Myoung;Seo, Kwang-Yell;Kim, Joo-Yeon;Kim, Byung-Cheul
    • Transactions on Electrical and Electronic Materials
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    • v.7 no.4
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    • pp.180-183
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    • 2006
  • We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

Highly Integrated 3-dimensional NOR Flash Array with Vertical 4-bit SONOS (V4SONOS) (수직형 4-비트 SONOS를 이용한 고집적화된 3차원 NOR 플래시 메모리)

  • Kim, Yoon;Yun, Jang-Gn;Cho, Seong-Jae;Park, Byung-Gook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.1-6
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    • 2010
  • We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.

Fabrication of Tern bit level SONOS F1ash memories (테라비트급 SONOS 플래시 메모리 제작)

  • Kim, Joo-Yeon;Kim, Byun-Cheul;Seo, Kwang-Yell;Kim, Jung-Woo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.26-27
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    • 2006
  • To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

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Investigation for Multi-bit per Cell on the CSL-NOR Type SONOS Flash Memories (CSL-NOR형 SONOS 플래시 메모리의 멀티비트 적용에 관한 연구)

  • Kim Joo-Yeon;An Ho-Myoung;Lee Myung-Shik;Kim Byung-Cheul;Seo Kwang-Yell
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.3
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    • pp.193-198
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    • 2005
  • NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

The Write Characteristics of SONOS NOR-Type Flash Memory with Common Source Line (공통 소스라인을 갖는 SONOS NOR 플래시 메모리의 쓰기 특성)

  • An, Ho-Myoung;Han, Tae-Hyeon;Kim, Joo-Yeon;Kim, Byung-Cheul;Kim, Tae-Geun;Seo, Kwang-Yell
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.35-38
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    • 2002
  • In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride, and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

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A study on the programming conditions suppressing the lateral diffusion of charges for the SONOS two-bit memory (SONOS two-bit 메모리의 측면확산에 영향을 주는 programming 조건 연구)

  • Lee, Myung-Shik;An, Ho-Myung;Seo, Kwang-Yell;Koh, Jung-Hyuk;Kim, Byung-Cheul;Kim, Joo-Yeon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.117-120
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    • 2005
  • The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

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Fabrication and Device Performance of Tera Bit Level Nano-scaled SONOS Flash Memories (테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가)

  • Kim, Joo-Yeon;Kim, Moon-Kyung;Kim, Byung-Cheul;Kim, Jung-Woo;Seo, Kwang-Yell
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.20 no.12
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    • pp.1017-1021
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    • 2007
  • To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

  • An, Ho-Myoung;Kim, Byungcheul
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.1
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    • pp.25-28
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    • 2016
  • We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 102 program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 103 P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×1011 cm−2 for the initial state to 4×1012 cm−2 for 102 P/E cycles. Over 103 P/E cycles, the Nit increased dramatically from 5.51×1012 cm−2 for 103 P/E cycles to 5.79×1012 cm−2 for 104 P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays.