Browse > Article
http://dx.doi.org/10.4313/JKEM.2005.18.3.193

Investigation for Multi-bit per Cell on the CSL-NOR Type SONOS Flash Memories  

Kim Joo-Yeon (울산과학대학 전기전자통신학부 반도체응용전공)
An Ho-Myoung (광운대학교 전자재료공학과)
Lee Myung-Shik (광운대학교 전자재료공학과)
Kim Byung-Cheul (진주산업대학교 전자공학과)
Seo Kwang-Yell (광운대학교 전자재료공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.18, no.3, 2005 , pp. 193-198 More about this Journal
Abstract
NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.
Keywords
SONOS; NOR type flash memory; Common source line; Multi-bit; Charge pumping method;
Citations & Related Records
연도 인용수 순위
  • Reference
1 The International Technology Roadmap for Semiconductor(ITRS), table 38a, 2001
2 B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, 'NROM: a novel localized trapping, 2-bit nonvolatile memory cell', IEEE Electron Device Letters, Vol. 21, No. 11, p. 543, 2000   DOI   ScienceOn
3 Chun Chen and Tso-Ping Ma, 'Direct lateral profile of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET's', IEEE Trans. Electron Dev., Vol. 45, No. 11, p. 512, 1998
4 S. Tiwari et al. 'A silicon nanocrystals based memory', Appl. Phys. Lett. Vol. 68, p, 1377, 1996   DOI
5 H. A. R. Wegener, A. J Lincoln, H. C. Pao, M. R. O'Connell, and R. E. Oleksiak, 'The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device', IEEE IEDM Tech. Dig., Washington, D. C., p, 70, 1967
6 F. L. Hampton and J. R. Cricchi, 'Space charge distribution limitation on scale down of MNOS memory devices', IEEE IEDM Tech. Dig., p. 374, 1979
7 Ho-Myoung An, Myung-Shik Lee, KwangYell Seo, Byoung-Cheul Kim, and Joo- Yeon Kim, 'An investigation of locally trapped charge distribution using the charging pumping method in the two-bit SONOS cell', Trans. EEM, Vol. 5, No.4, p. 148, 2004
8 김주연, 'SONOS구조를 갖는 멀티비트 소자의 프로그램 특성', 전기전자재료학회논문지, 16권 9호, p. 771, 2003