• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.387-394
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• 2005

In order to design SOI CMOS image sensors, SOI MOSFET model parameters were extracted using the equation of bulk MOSFET model parameters and were optimized using SPICE level 2. Simulated I-V characteristics of the SOI NMOSFET using the extracted model parameters were compared to the experimental I-V characteristics of the fabricated SOI NMOSFET. The simulation results agreed well with experimental results. A unit pixel for SOI CMOS image sensors was designed and was simulated for the PPS, APS, and logarithmic circuit using the extracted model parameters. In these CMOS image sensors, a nano-wire MOSFET photodetector was used. The output voltage levels of the PPS and APS are well-defined as the photocurrent varied. It is confirmed that SOI CMOS image sensors are faster than bulk CMOS image sensors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.583-590
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• 2002

In this paper, a new Silicon on Insulator (SOI)-based photodetector was proposed, and its basic operation principle was explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) which are three primary colors of light can be realized without using any organic color filters. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector. To see the response characteristics to the green (G) among RGB, SOI and bulk NMOSFETS were fabricated using $1.5\mu m$ CMOS technology and characterized. We obtained optimum optical response characteristics at $V_{GS}=0.35 V$ in NMOSFET with threshold voltage of 0.72 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. The SOI and the bulk NMOSFETS shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.28-36
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• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.21-27
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• 2015

An improved method based on direct extraction and simultaneous optimization is developed to determine model parameters of symmetric inductors fabricated by the high resistivity(HR) silicon-on-insulator(SOI) RF CMOS process. In order to improve modeling accuracy, several model parameters are directly extracted by Y and Z-parameter equations derived from two equivalent circuits of symmetric inductor and grounded center-tap one, and the number of unknown parameters is reduced using parallel resistance and total inductance equations. In order to improve optimization accuracy, two sets of measured S-parameters are simultaneously optimized while same model parameters in two equivalent circuits are set to common variables.

• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Journal of IKEEE
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• v.20 no.3
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.