[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.7471/ikeee.2016.20.3.279

An L-band Stacked SOI CMOS Amplifier

Kim, Young-Gi (Dept. of Information and Communication Engineering, Anyang University)
Hwang, Jae-Yeon (Dept. of Information and Communication Engineering, Anyang University)

Publication Information

Journal of IKEEE / v.20, no.3, 2016 , pp. 279-284 More about this Journal

Abstract

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$ .

Keywords

SOI CMOS; L-band amplifier; stack FET amplifier; CMOS-MMIC; Silicon-On-Insulator (SOI); stacked transistors; CMOS amplifier;

Citations & Related Records

Reference

1	I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, "Fully integrated CMOS power amplifier design using the distributed active-transformer architecture," IEEE Journal of Solid-State Circuits, vo. 37, no. 3, pp. 371-383, Mar. 2002. DOI
2	Niknejad, A. M., Chowdhury, D. Jiashu Chen, "Design of CMOS Power Amplifiers," IEEE Trans. Microwave Theory and Techniques, vo. 60, no. 6, pp. 1784 - 1796, Jun. 2012. DOI
3	G. G. Shahidi, "SOI technology for the GHz era," IBM J. RES. & DEV., vo. 46, no. 2/3, pp. 121-131, Mar. 2002. DOI
4	I. Aoki, S. D. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, and A. Hajimiri, "A fully integrated quadband GSM/GPRS CMOS power amplifier," IEEE Journal of Solid-State Circuits, vo. 43, no. 12, pp. 2747-2758, Dec. 2008. DOI
5	T. Sowlati and D. M. W. Leenaerts, "A 2.4-GHz $0.18-{\mu}m$ CMOS self biased cascode power amplifier," IEEE Journal of Solid-State Circuits, vo. 38, no. 8, pp. 1318-1324, Aug. 2003. DOI
6	S. Pompromlikit, J. Jeong, C. D. Presi, A. Scuderi, and P. Asbeck, "A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS," IEEE Trans. Microwave Theory and Techniques, vo. 58, no. I, pp. 57-64, Jan. 2010. DOI
7	C. Jing-Hwa, S. R. Helmi, H. Pajouhi, S. Yukeun, and S. Mohammadi, "A 1.8GHz stacked power amplifier in 45nm CMOS SOI technology with substrate-transferred to AlN," in Proc. of the 2012 IEEE MTT-S Microwave Symposium Digest, pp. 1-3, 2012.
8	J. Jayman. A. Agah, B. Hanafi, H. Dabag, J. Buckwalter and P. Asbeck. "A W-band Stacked FET Power Amplifier with 17 dBm Psat in 45-nm SOI CMOS," in Proc. of the 2013 IEEE Radio and Wireless Symposium (RWS), 2013, pp. 256-258.
9	S. Leuschner, J. E. Mueller, H. Klar, "A 1.8GHz wide-band stacked-cascode CMOS power amplifier for WCDMA applications in 65nm standard CMOS," in Proc. of the 2011 IEEE Radio Frequency Integrated Circuits Symp., June. 2011, pp. 1-4.
10	C. Wang, M. Vaidyanathan, and L. E. Larson, "A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers," IEEE Journal of Solid-State Circuits, vo. 39, no. 11, pp. 1927-1937, Nov. 2004. DOI
11	H. Jeon, K.-S. Lee, O. Lee, K. H. An, Y. Yoon, H. Kim, D. H. Lee, J. Lee, C.-H. Lee, and J. Laskar, "A 40% PAE Linear CMOS Power Amplifier with Feedback Bias Technique for WCDMA Applications," in Proc. of the 2010 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2010, pp. 561-564.