• Analytical Science and Technology
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• v.13 no.3
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• pp.368-377
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• 2000

Si-immobilized Sargassum horneri was used to study the adsorption characteristics along with maximum adsorption conditions of heavy metal ions, Cd(II) and Ph(II) on the Si-immobilized Sargassum horneri. More amount of Cd(II) and Pb(II) ions on the Si-immobilized Sargassum horneri than Sargassum horneri were adsorbed. And Pb(II) ions were more adsorbed in all algae than Cd(II) ions more effectively in alkaline than in acidity. Recovery ratios of Cd(II) and Pb(II) ions on the Sargassum horneri were 58.0-62.6%, 61.2-64.4% respectively, Si-immobilized Sargassum horneri 56.8-92.7%, 37.8-47.9%. Recovery ratio of Cd(II) ion was higher on the Si-immobilized Sargassum horneri but it of Pb(II) ion was lower on the Si-immobilized Sargassum horneri.

• Journal of the Korean Chemical Society
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• v.56 no.4
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• pp.448-458
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• 2012

In order to develop alloy resistance in aggressive sulphat ion, the corrosion behavior of metallic glasses $Ni_{92{\cdot}3}Si_{4.5}B_{32}$, $Ni_{82,3}Cr_7Fe_3Si_{4.5}B_{3.2}$ and $Ni_{75.5}Cr_{13}Fe_{4.2}Si_{4.5}B_{2.8}$ (at %) at different concentrations of $H_2SO_4$ solutions was examined by electrochemical methods and Scanning Electron Microscope (SEM) and X-ray Photoelectron Microscopy (XPS) analyses. The corrosion kinetics and passivation behavior was studied. A direct proportion was observed between the corrosion rate and acid concentration in the case of $Ni_{92{\cdot}3}Si_{4.5}B_{32}$ and $Ni_{75.5}Cr_{13}Fe_{4.2}Si_{4.5}B_{2.8}$ alloys. Critical concentration was observed in the case of $Ni_{82,3}Cr_7Fe_3Si_{4.5}B_{3.2}$ alloy. The influence of the alloying element is reflected in the increasing resistance of the protective film. XPS analysis confirms that the protection film on the $Ni_{92{\cdot}3}Si_{4.5}B_{32}$ alloy was NiS which is less protective than that formed on Cr containing alloys. The corrosion rate of $Ni_{82,3}Cr_7Fe_3Si_{4.5}B_{3.2}$ and $Ni_{75.5}Cr_{13}Fe_{4.2}Si_{4.5}B_{2.8}$. alloys containing 7% and 13% Cr are $7.90-26.1{\times}10^{-3}$ mm/y which is lower about 43-54 times of the alloy $Ni_{92{\cdot}3}Si_{4.5}B_{32}$ (free of Cr). The high resistance of $Ni_{75.5}Cr_{13}Fe_{4.2}Si_{4.5}B_{2.8}$ alloy at the very aggressive media may due to thicker passive film of $Cr_2O_3$ which hydrated to hydrated chromium oxyhydroxide.

• Journal of Ocean Engineering and Technology
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• v.22 no.5
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• pp.106-111
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• 2008

In this paper, study about property evaluation for the metal matrix composites fabricated by low pressure infiltration process. Aluminum alloy composite which is reinforced by Metal fiber preform was fabricated by low pressure casting process. Infiltration condition was changed the pressure infiltration time of 1 sec, 2 sec and 5 sec under a constant pressure of 0.4 MPa. The molten alloy completely infiltrated the FeCrSi metal perform regardless of the increase in the pressure acceleration time. The the porosity in the FeCrSi/AC8A composite was investigated. The porosity was reduced as the pressure acceleration time as shorter. The FeCrSi/AC8A composite was investigated the wear test for to know the relationship between Porosity and wear resistance. FeCrSi/AC8A composite at pressure acceleration time of 1sec is shown excellent wear resistance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.13-20
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• 2008

This paper describes the methods of spacer-fabrication for wafer-level CIS(CMOS Image Sensor) assembly. We propose three methods using SU-8, PDMS and Si-interposer for the spacer-fabrication. For SU-8 spacer, novel wafer rotating system is developed and for PDMS(poly-dimethyl siloxane) spacer, new fabrication-method is used to bond with alignment of glass/PDMS/glass structure. And for Si-interposer, DFR(Dry Film Resist) is used as adhesive layer. The spacer using Si-interposer has the strongest bonding strength and the strength is 32.3MPa with shear.

• Journal of the Korean Vacuum Society
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• v.15 no.3
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• pp.273-279
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• 2006

This study explored the possibility of porous Si (PS) formed by indirect electrode anodization used for effective isolation material for radio frequency integrated circuits (RFIC). We investigated the effect of current density and reaction time on the porosity size and depth, and X-ray diffraction of bulk Si and porous Si to evaluate the change in lattice parameter. Porosity size and depth usually increases with an increase in the current density and reaction time. PS increases the lattice parameter of Si compared to the bulk Si which causes the compressive stress of around 8 MPa. PS formed by the method is believed to be suitable for isolation material for RFIC because it is simple process as well as good compatibility to Si VLSI process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.8
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• pp.732-736
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• 2006

This paper describes the physical characterizations of polycrystalline 3C-SiC thin films heteroepitaxially grown on Si wafers with thermal oxide, In this work, the 3C-SiC film was deposited by LPCVD (low pressure chemical vapor deposition) method using single precursor 1, 3-disilabutane $(DSB:\;H_3Si-CH_2-SiH_2-CH_3)\;at\;850^{\circ}C$. The crystallinity of the 3C-SiC thin film was analyzed by XPS (X-ray photoelectron spectroscopy), XRD (X-ray diffraction) and FT-IR (fourier transform-infrared spectometers), respectively. The surface morphology was also observed by AFM (atomic force microscopy) and voids or dislocations between SiC and $SiO_2$ were measured by SEM (scanning electron microscope). Finally, residual strain was investigated by Raman scattering and a peak of the energy level was less than other type SiC films, From these results, the grown poly 3C-SiC thin film is very good crystalline quality, surface like mirror, and low defect and strain. Therefore, the polycrystalline 3C-SiC is suitable for harsh environment MEMS (Micro-Electro-Mechanical-Systems) applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.357-358
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• 2007

Raman spectra of poly (polycrystalline) 3C-SiC thin films, which were deposited on the oxidized Si substrate by APCVD, have been measured. They were used to study the mechanical characteristics of poly 3C-SiC grown in various temperatures. TO and LO modes of 2.0 m poly 3C-SiC grown at 1180 C occurred at 794.4 and $965.7\;cm^{-1}$. Their FWHMs (full width half maximum) were used to investigate the stress and the disorder of 3C-SiC. The broad FWHM can explain that the crystallinity of 3C-SiC grown at 1180 C becomes poly crystalline instead of the disordered crystal. The ratio of intensity $I_{(LO)}/I_{(TO)}$ 1.0 means that the crystal defect of 3C-SiC/$SiO_2$/Si is small. The biaxial stress of poly 3C-SiC was obtained as 428 MPa. In the interface of 3C-SiC/$SiO_2$, the phonon mode of C-O bonding appeared at $1122.6\;cm^{-1}$. The phonon modes related to D and G bands of C-C bonding were measured at 1355.8 and $1596.8\;cm^{-1}$ respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.576-581
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• 2005

In this paper. the a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. High k gate dielectric is required for on-current, threshold voltage and breakdown characteristics of TFT Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_3N_4$. Ferroelectric increases on-current and decreases threshold voltage of TFT and also ran improve breakdown characteristics.$SrTiO_4$ thin film is deposited by e-beam evaporation. Deposited films are annealed for 1 hour in N2 ambient at $150^{\circ}C\~600^{\circ}C$. Dielectric constant of ferroelectric is about 60-100 and breakdown field is about IMV/cm. In this paper, the TFT using ferroelectric consisted of double layer gate insulator to minimize the leakage current. a-SiN:H, a-Si:H (n-type a-Si:H) are deposited onto $SrTiO_3$ film to make MFNS(Metal/ferroelectric/a-SiN:H/a-Si:H) by PECVD. In this paper, TFR using ferroelectric has channel length of$8~20{\mu}m$ and channel width of $80~200{\mu}m$. And it shows that drain current is $3.4{\mu}A$at 20 gate voltage, $I_{on}/I_{off}$ is a ratio of $10^5\~10^8,\;and\;V_{th}$ is$4\~5\;volts$, respectively. In the case of TFT without having ferroelectric, it indicates that the drain current is $1.5{\mu}A$ at 20gate voltage and $V_{th}$ is $5\~6$ volts. If properties of the ferroelectric thin film are improved, the performance of TFT using this ferroelectric thin film can be advanced.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.57-64
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• 2007

New Chip-on-glass technology to attach an Si chip directly on the glass substrate of LCD panel was studied with local heating method of the Si chip by using thin film heater fabricated on the Si chip. Square-shaped Cu thin film heater with the width of $150\;{\mu}m$, thickness of $0.8\;{\mu}m$, and total length of 12.15 mm was sputter-deposited on the $5\;mm{\times}5\;mm$ Si chip. With applying current of 0.9A for 60 sec to the Cu thin film heater, COG bonding of a Si chip to a glass substrate was successfully accomplished with reflowing the Sn-3.5Ag solder bumps on the Si chip.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.