• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.19-26
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• 2020

Steel production requires high-quality surfaces with minimal defects. Therefore, the detection algorithms for the surface defects of steel strip should have good generalization performance. To meet the growing demand for high-quality products, the use of intelligent visual inspection systems is becoming essential in production lines. In this paper, we proposed a ShuffleDefectNet defect detection system based on deep learning. The proposed defect detection system exceeds state-of-the-art performance for defect detection on the Northeastern University (NEU) dataset obtaining a mean average accuracy of 99.75%. We train the best performing detection with different amounts of training data and observe the performance of detection. We notice that accuracy and speed improve significantly when use the overall architecture of ShuffleDefectNet.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.1064-1074
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• 1997

In this paper we propose an every-other-row-connecting bilayered ShuffkeNet for optical WDM(wavelength division multiplexing) multihop networks. We calculate the diameter and the average number of hops of the proposed every-other-row-connecting bilayered ShuffleNet. Using the result, we also calcuate throughputs and delays of the proposed topology, which show higher efficiencies compared to the conventional ShuffleNet, the bilayered ShuffleNet and asymmetric bilayered ShuffleNet.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.355-361
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• 1987

The shuffle-exchange graph is known as a structure to perform the parallel algorithms like Discrete Fourier Transform(DFT), matrix multiplication and sorting. In this paper, the layout for the shuffle-exchange graph is described and this layout places emphasis on the placement of nodes that has the capability to have as small area as possible, have as a small number of crossings as possible, and have as short wires as possible. The algorithm corrdsponding these conditions is proposed and each evaluation factor and the placement of the N-node shuffle-exchange graph is performed with FORTRAN and BASIC program, and these results are calcualted.

• KIISE Transactions on Computing Practices
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• v.23 no.12
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• pp.677-683
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• 2017

Apache Storm is a representative real-time distributed processing system, which is able to process data streams quickly over distributed servers. Storm currently provides several stream grouping methods to distribute data traffic to multiple servers. Among them, the shuffle grouping may cause a processing delay problem and the local-or-shuffle grouping used to solve the problem may cause the problem of concentrating the traffic on a specific node. In this paper, we propose the locality-aware grouping to solve the problems that may arise in the existing Storm grouping methods. Experimental results show that the proposed locality-aware grouping is considerably superior to the existing shuffle grouping and the local-or-shuffle grouping. These results show that the new grouping is an excellent approach considering both the locality and load balancing which are limitations of the existing Storm.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.107-116
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• 2007

In this paper, we present a method on the construction of multiple-valued circuits using Reed-Muller Expansions(RME). First, we discussed the input output interconnection of multiple valued function using Perfect Shuffle techniques and Kronecker product and designed the basic cells of performing the transform matrix and the reverse transform matrix of multiple valued RME using addition circuit and multiplication circuit of GF(4). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the multiple valued logic circuit based on RME. The proposed design method of multiple valued RME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same function because of using matrix transform based on modular structures. The proposed design method of multiple valued logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

• Nuclear Engineering and Technology
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• v.54 no.8
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• pp.3176-3180
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• 2022

A gamma irradiator is a well-developed installation for gamma radiation sterilization. A "shuffle-dwell" mode is preferable for high dose applications. A novel configuration of a shuffle-dwell gamma irradiator is proposed to increase energy utilization and throughput, which would result in higher profitability. While the minimum distance between any irradiation position and each source pencil, the minimum distance between the neighboring irradiation positions and the size of source pencils are kept the same as the current configuration, the irradiation positions and source pencils are rearranged based on the fact that radiation is emitted in an isotropic fashion. The computational results suggest that the proposed configuration requires an 8.7% smaller area and exposes the product to 11.8% more gamma radiation in a 10.7% shorter irradiation time. In other words, the proposed configuration needs a smaller area and shorter irradiation time to have a better performance compared to the current shuffle-dwell gamma irradiator. Note that the claim is based primarily on an analytical calculation. Experimental and manufacturing among other practical considerations will be taken into account in the future work to exhaustively evaluate the performance of the proposed configuration and to compare it with that of the traditional configuration.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1842-1850
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• 1997

This paper proposes a new rearrangeable algorithm in multistage reverse shuffle/exchange network. The best known lower bound of stages for rearrangeability in symmetric network is 2logN-1 stages. However, it has never been proved for nonsymmetric networks before. Currently, the best upper bound for the rearrangeability of a shuffle/exchange network in nonsymmetric network is 3logN-3 stages. We describe the rearrangeability of reverse shuffle/exchange multistage interconnection network on every arbitrary permutation with $N{\le}16$. This rearrangeability can be established by setting one more stages in the middle stage of the network to allow the reduced network to be topological equivalent to a class of rearrangeable networks. The results in this paper enable us to establish an upper bound, 2logN stages for rearrangeable reverse shuffle/exchange network with $N{\le}16$, and leads to the possibility of this bound when $N{\le}16$.