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http://dx.doi.org/10.12673/jant.2018.22.5.429

Scalable FFT Processor Based on Twice Perfect Shuffle Network for Radar Applications  

Kim, Geonho (School of Electronics and Information Engineering, Korea Aerospace University)
Heo, Jinmoo (School of Electronics and Information Engineering, Korea Aerospace University)
Jung, Yongchul (School of Electronics and Information Engineering, Korea Aerospace University)
Jung, Yunho (School of Electronics and Information Engineering, Korea Aerospace University)
Publication Information
Journal of Advanced Navigation Technology / v.22, no.5, 2018 , pp. 429-435 More about this Journal
Abstract
In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.
Keywords
Fast Fourier transform; Perfect shuffle network; Radar system; Radix-4;
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1 A. Boughambouz, A. Bellabas, B. Magaz, T. Menni, and M. Abdelaziz, "Improvement of radar signal phase extraction using All Phase FFT spectrum analysis," in Detection Systems Architectures and Technologies Seminar, Algiers: Algeria, Feb. 2017.
2 S. Saponara and B. Neri, “Radar sensor signal acquisition and multidimensional FFT processing for surveillance applications in transport systems,” IEEE Transactions on Instrumentation and Measurement, Vol. 66, No. 4, pp. 604-615, April 2017.   DOI
3 H. Stone, "Parallel processing with the perfect shuffle," IEEE Transaction on Computers, Vol. C-20, No.2, pp. 156-161, Feb. 1971.
4 V. Boriakoff, “FFT computation with Systolic arrays, a new architecture,” IEEE Transaction on Circuit and Systems, Analog and Digital Signal Processing, Vol. 41, No. 4, pp. 278-284, April. 1994.
5 A. Suleiman, A. Hussein, K. Bataineh, and D. Akopian, "Scalable FFT architecture vs. multiple pipeline FFT architectures-hardware implementation and cost," in Proceeding of the IEEE International Conference on Systems, Man and Cybernetics, San Antonio: TX, pp. 3792-3796, Oct. 2009.
6 M. H. Hwang and H, J. Hwang, "Design of radix-4 FFT processor using twice perfect shuffle," Journal of the Institute of Electronics and Information Engineers, Vol. 27, No.2, pp. 307-313, Feb. 1990.
7 S. Jardak, S. Ahmed, and M.S. Alouini, “Low complexity moving target parameter estimation for MIMO radar using 2D-FFT,” IEEE Transaction on Signal Processing, Vol. 65, No. 18, pp. 4745-4755, Sep. 2017.   DOI
8 E. Richter, R. Schubert, and G. Wanielik, "Radar and vision based data fusion-Advanced filtering techniques for a multi object vehicle tracking system," in Proceedings of the IEEE Intelligent Vehicles Symposium, Eindhoven: Netherlands, pp. 120-125, Jun. 2008.
9 M. Abe, "Trends of Intelligent Vehicle Dynamics Controls and Their Future," New Technology Network Technical Review, No. 81, pp. 2-11, 2013.
10 T. Hanke, N. Hirsenkorn, B. Dehlink, A. Rauch, R. Rasshofer, and E. Biebl, "Generic architecture for simulation of ADAS sensors," in Proceeding of the 16th International Radar Symposium (IRS), Dresden: Germany, pp. 125-130, Aug. 2015.
11 U. Kadow, G. Schneider, and A. Vukotich, "Radar-vision based vehicle recognition with evolutionary optimized and boosted features," in Proceedings of the IEEE Intelligent Vehicles Symposium, Istanbul: Turkey, pp. 749-754, Jun. 2007.