References
- S. L. Hurst, 'Multiple-Valued Logic-Its Status and Future,' IEEE Trans. Comput., Vol.C-30, No.9, pp.619-634, Sept., 1981 https://doi.org/10.1109/TC.1981.1675860
- B. Benjauthrit and I. S. Reed, 'Galois Switching Functions and Their Application,' IEEE Trans.Comput., Vol.C-25, No.1, pp.78-86, Jan. 1976 https://doi.org/10.1109/TC.1976.5009207
- J. T. Butler and A. S. Wojcik, 'Guest Editors' Comments,' IEEE Trans.Comput., Vol.C-30, No.9, pp.617-618, Sept., 1981 https://doi.org/10.1109/TC.1981.1675859
- H. T. Kung, 'Why Systolic Architectures?,' IEEE Computer, Vol.15, pp.37-46, Jan., 1982 https://doi.org/10.1109/MC.1982.1653825
- H. M. Shao, T. K. Truoung, L. J. Deutsch, J. H. Yaeh and I. S. Reed, 'A VLSI Design of a Pipelining Reed-Solomon Decoder,' IEEE Trans.Comput., Vol.C-34, No.5, pp.393-403, May, 1985 https://doi.org/10.1109/TC.1985.1676579
-
H. Y. Seong and H. S. Kim, 'A Construction of Cellular Array Multiplier over
$GF(2^m)$ ,' KITE, Vol.26, No.4, pp.81-87, April, 1989 - I. S. Hsu, T. K. Truong, L. T. Deutsch and I. S. Reed, 'A Comparison of VLSI Architecture of Finite Field Multiplier Using Dual, Normal, or Standard Bases,' IEEE Trans. Comput., Vol.C-37, No.6, pp.735-739, June,1988 https://doi.org/10.1109/12.2212
-
B. B. Zhou, 'A New Bit-Serial Systolic Multiplier over
$GF(2^m)$ ,' IEEE Trans.Comput., Vol.C-37, No.6, pp.749-751, June, 1988 https://doi.org/10.1109/12.2216 - J. M. Pollard, 'The Fast Fourier Transform in a Finite Field,' Math. Comput., Vol.25, No.114, pp.365-374, April, 1971 https://doi.org/10.2307/2004932
- Y. Wang and X. Zhu, 'A Fast Algorithm for the Fourier Transform over Finite Field and Its VLSI Implementation,' IEEE J. Select. Area Commu., Vol.6, No.3, pp.573-577, April, 1988 https://doi.org/10.1109/49.1926
- F. Yang, 'Fast Synthesis of Q-valued Functions Based on Modulo Algebra Expansions,' Proc. of 16th International Symposium on Multiple-Valued Logic, Virginia, USA, pp.36-41, May, 1986
- E. N. Zaitseva, T. G. Kalganova, and E. G. Kochergov, 'Logical not Polynomial Forms to represent Multiple-Valued Functions,' Proc. of 26th International Symposium on Multiple-Valued Logic, Santiago de Compostela, Spain, pp.302-307, May, 1996 https://doi.org/10.1109/ISMVL.1996.508378
- R. S. Stankovic and C. Moraga, 'Reed-Muller-Fourier Versus Galois Field Representations of Four-Valued Logic Functions,' Proc. of 28th International Symposium on Multiple-Valued Logic, Fukuoka, Japan, pp.186-191, May, 1998 https://doi.org/10.1109/ISMVL.1998.679340
- R. S. Stankovic and J. Astola, 'Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies,' Proc. of 31st International Symposium on Multiple-Valued Logic, Warsaw, Poland, pp.305-310, May, 2001 https://doi.org/10.1109/ISMVL.2001.924588
- S. Rahardja and B. J. Falkowski, 'A New Algorithm to Compute Quarternary Reed-Muller Expansions,' Proc. of 30th International Symposium on Multiple-Valued Logic, Portland, Oregon, pp.153-158, May, 2000 https://doi.org/10.1109/ISMVL.2000.848614
- B. Harking and C. Moraga, 'Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems,' Proc. of 22nd International Symposium on Multiple-Valued Logic, pp.436-441, May, 1992 https://doi.org/10.1109/ISMVL.1992.186828
- M. Davio, 'Kronecker Products and Shuffle Algebra,' IEEE Trans. Comput., Vol.C-30, No.2, pp.116-125, Feb., 1981 https://doi.org/10.1109/TC.1981.6312174
- T. Y. Feng, 'A Survey of Interconnection Networks,' IEEE Computer, Vol.14, No.10, pp.12-27, Dec., 1981 https://doi.org/10.1109/C-M.1981.220290
- C. L. Wu and T. U. Feng, 'On a Class of Multistage Interconnection Networks,' IEEE Trans. Comput., Vol.C-29, No.8, pp.694-702, Aug., 1980 https://doi.org/10.1109/TC.1980.1675651