Browse > Article
http://dx.doi.org/10.3745/KIPSTA.2002.9A.3.271

Design of Multiple-Valued Logic Circuits on Reed-Muller Expansions Using Perfect Shuffle  

Seong, Hyeon-Gyeong (상지대학교 컴퓨터·정보공학부)
Publication Information
The KIPS Transactions:PartA / v.9A, no.3, 2002 , pp. 271-280 More about this Journal
Abstract
In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.
Keywords
Perfect Shuffle; multiple-valued logic circuits; Kronecker product; Multiple-Valued Reed-Muller expansions;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 I. S. Hsu, T. K. Truong, L. T. Deutsch and I. S. Reed, 'A Comparison of VLSI Architecture of Finite Field Multiplier Using Dual, Normal, or Standard Bases,' IEEE Trans. Comput., Vol.C-37, No.6, pp.735-739, June,1988   DOI   ScienceOn
2 S. L. Hurst, 'Multiple-Valued Logic-Its Status and Future,' IEEE Trans. Comput., Vol.C-30, No.9, pp.619-634, Sept., 1981   DOI   ScienceOn
3 B. Benjauthrit and I. S. Reed, 'Galois Switching Functions and Their Application,' IEEE Trans.Comput., Vol.C-25, No.1, pp.78-86, Jan. 1976   DOI   ScienceOn
4 J. T. Butler and A. S. Wojcik, 'Guest Editors' Comments,' IEEE Trans.Comput., Vol.C-30, No.9, pp.617-618, Sept., 1981   DOI   ScienceOn
5 H. T. Kung, 'Why Systolic Architectures?,' IEEE Computer, Vol.15, pp.37-46, Jan., 1982   DOI   ScienceOn
6 H. M. Shao, T. K. Truoung, L. J. Deutsch, J. H. Yaeh and I. S. Reed, 'A VLSI Design of a Pipelining Reed-Solomon Decoder,' IEEE Trans.Comput., Vol.C-34, No.5, pp.393-403, May, 1985   DOI   ScienceOn
7 H. Y. Seong and H. S. Kim, 'A Construction of Cellular Array Multiplier over $GF(2^m)$,' KITE, Vol.26, No.4, pp.81-87, April, 1989   과학기술학회마을
8 B. B. Zhou, 'A New Bit-Serial Systolic Multiplier over $GF(2^m)$,' IEEE Trans.Comput., Vol.C-37, No.6, pp.749-751, June, 1988   DOI   ScienceOn
9 J. M. Pollard, 'The Fast Fourier Transform in a Finite Field,' Math. Comput., Vol.25, No.114, pp.365-374, April, 1971   DOI
10 Y. Wang and X. Zhu, 'A Fast Algorithm for the Fourier Transform over Finite Field and Its VLSI Implementation,' IEEE J. Select. Area Commu., Vol.6, No.3, pp.573-577, April, 1988   DOI   ScienceOn
11 F. Yang, 'Fast Synthesis of Q-valued Functions Based on Modulo Algebra Expansions,' Proc. of 16th International Symposium on Multiple-Valued Logic, Virginia, USA, pp.36-41, May, 1986
12 E. N. Zaitseva, T. G. Kalganova, and E. G. Kochergov, 'Logical not Polynomial Forms to represent Multiple-Valued Functions,' Proc. of 26th International Symposium on Multiple-Valued Logic, Santiago de Compostela, Spain, pp.302-307, May, 1996   DOI
13 R. S. Stankovic and C. Moraga, 'Reed-Muller-Fourier Versus Galois Field Representations of Four-Valued Logic Functions,' Proc. of 28th International Symposium on Multiple-Valued Logic, Fukuoka, Japan, pp.186-191, May, 1998   DOI
14 S. Rahardja and B. J. Falkowski, 'A New Algorithm to Compute Quarternary Reed-Muller Expansions,' Proc. of 30th International Symposium on Multiple-Valued Logic, Portland, Oregon, pp.153-158, May, 2000   DOI
15 B. Harking and C. Moraga, 'Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems,' Proc. of 22nd International Symposium on Multiple-Valued Logic, pp.436-441, May, 1992   DOI
16 M. Davio, 'Kronecker Products and Shuffle Algebra,' IEEE Trans. Comput., Vol.C-30, No.2, pp.116-125, Feb., 1981   DOI   ScienceOn
17 T. Y. Feng, 'A Survey of Interconnection Networks,' IEEE Computer, Vol.14, No.10, pp.12-27, Dec., 1981   DOI   ScienceOn
18 R. S. Stankovic and J. Astola, 'Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies,' Proc. of 31st International Symposium on Multiple-Valued Logic, Warsaw, Poland, pp.305-310, May, 2001   DOI
19 C. L. Wu and T. U. Feng, 'On a Class of Multistage Interconnection Networks,' IEEE Trans. Comput., Vol.C-29, No.8, pp.694-702, Aug., 1980   DOI   ScienceOn