• Journal of KIISE:Software and Applications
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• v.29 no.4
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• pp.225-234
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• 2002

The developers of mobile agent systems are considering integrating the system into the web and the developers of web servers are also considering supporting mobile agents in the future. But they are not clearly suggesting the relationship between web programming which has basically client/server architecture and mobile agent programming which is based on autonomous code mobility. In this paper, firstly, we clarify the method for integrating mobile agent programming into web programming by suggesting the model for mobile agent programming on the web. Secondly, by developing APIs for Java which is widely used for both web programming and mobile agent programming, we made it possible for programmers to use them for programming mobile agent on the web. Thirdly, we show the usefulness of the proposed model by adding and testing modules for execution environment of mobile agents on W3C's Java based web server, Jigsaw.

• International Journal of Naval Architecture and Ocean Engineering
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• v.9 no.5
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• pp.552-567
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• 2017

The floating crane vessel in waves gives rise to the motion of the lifted object which is connected to the hoisting wire. The dynamic tension induced by the lifted object also affects the motion responses of the floating crane vessel in return. In this study, coupled motion responses of a floating crane vessel and a lifted subsea manifold during deep-water installation operations were investigated by both experiments and numerical calculations. A series of model tests for the deep-water lifting operation were performed at Ocean Engineering Basin of KRISO. For the model test, the vessel with a crane control system and a typical subsea manifold were examined. To validate the experimental results, a frequency-domain motion analysis method is applied. The coupled motion equations of the crane vessel and the lifted object are solved in the frequency domain with an additional linear stiffness matrix due to the hoisting wire. The hydrodynamic coefficients of the lifted object, which is a significant factor to affect the coupled dynamics, are estimated based on the perforation value of the structure and the CFD results. The discussions were made on three main points. First, the motion characteristics of the lifted object as well as the crane vessel were studied by comparing the calculation results. Second, the dynamic tension of the hoisting wire were evaluated under the various wave conditions. Final discussion was made on the effect of passive heave compensator on the motion and tension responses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.39-45
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• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.36-44
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• 2016

In this paper, an Impulse Radio-Ultra Wide band RF Transceiver for WBAN applications is implemented in $0.18{\mu}m$ CMOS technology. The designed RF transceiver support 3-5GHz UWB low band and employs OOK(On-Off Keying) modulation. The receiver employs non-coherent energy detection architecture to reduce complexity and power consumption. For the rejection of the undesired interferers and improvement of the receiver sensitivity, RF active notch filter is integrated. The VCO based transmitter employs the switch mechanism. As adapt the switch mechanism, power consumption and VCO leakage can be reduced. Also, the spectrum mask is always same at each center frequency. The measured sensitivity of the receiver is -84.1 dBm at 3.5 GHz with 1.579 Mbps. The power consumption of the transmitter and receiver are 0.3nJ/bit and 41 mW respectively.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

• Journal of the Korean Society of Safety
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• v.27 no.2
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• pp.49-56
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• 2012

If cement can be manufactured with industrial byproducts such as granulated blast furnace slag, phosphogypsum, and waste lime instead of clinker, there would be many advantages, including maximum use of these industrial byproducts for high value-added resources, conservation of natural resources and energy by omitting the use of clinker, minimized environmental pollution problems caused by CO2 discharge, and reduction of the production cost. By this reason, in this study, mechanical behavior tests of non-burnt cement concrete were performed, and elasticity modulus and stress-strain relationship of non-burnt cement concrete were proposed. 6 test members were manufactured and tested according to reinforcement ratio and concrete compressive strength. By the test results, there was no difference between ordinary concrete and non-burnt cement concrete of flexural behavior. In order to verify the proposed non-burnt cement concrete model, nonlinear analytical model was derived by using strain compatibility method. By the results of comparison between test results, ordinary concrete model and proposed model, The proposed model well predicted the flexural behavior of non-burnt cement concrete.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of Practical Agriculture & Fisheries Research
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• v.23 no.1
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• pp.13-26
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• 2021

This study was conducted to identify various types of activities of payment contract for ecosystem services. As supporting services, 12 types of activities were derived: fallow, eco-friendly crop cultivation, shelter creation management, etc. As regulating services, 5 types of activities were derived: stream environment purification, creation and management of riparian vegetation, creation and management of forests for responding to climate change, etc. As cultural services, five types of activities were derived: creation and management of landscape forests, creation and management of ecological trails, managing ecosystem conservation, etc.