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http://dx.doi.org/10.9723/jksiis.2015.20.4.039

A Design of Variable Rate Clock and Data Recovery Circuit for Biomedical Silicon Bead  

Cho, Sung-Hun (성균관대학교 정보통신대학)
Lee, Dong-Soo (성균관대학교 정보통신대학)
Park, Hyung-Gu (성균관대학교 정보통신대학)
Lee, Kang-Yoon (성균관대학교 정보통신대학)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.20, no.4, 2015 , pp. 39-45 More about this Journal
Abstract
In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.
Keywords
Clock and Data Recovery; Blind Oversampling; Variable Rate;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
연도 인용수 순위
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