A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS |
Kim, Sang-Yun
(College of Information and Communication Engineering, Sungkyunkwan University)
Lee, Juri (College of Information and Communication Engineering, Sungkyunkwan University) Park, Hyung-Gu (College of Information and Communication Engineering, Sungkyunkwan University) Pu, Young Gun (College of Information and Communication Engineering, Sungkyunkwan University) Lee, Jae Yong (College of Information and Communication Engineering, Sungkyunkwan University) Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University) |
1 | K. Hu et al., "A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-locked Ring Oscillators in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899-908, Apr. 2010. DOI ScienceOn |
2 | J.-K. Kim, J. Kim, G. Kim, and D.-K. Jeong, "A Fully Integrated 0.13-mm CMOS 40-Gb/s Serial Link Transceiver," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1510-1521, May. 2009. DOI ScienceOn |
3 | K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang, "A 27-mW 3.6-Gb/s I/O Transceiver," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 602-612, Apr. 2004. DOI ScienceOn |
4 | S. Lee et al., "A 2.7 Gbps & 1.62 Gbps Dual-mode Clock and Data Recovery for DisplayPort in 0.18 CMOS," in Proc. IEEE Int. SOC Conf., 2009, pp. 179-182. |
5 | K. Min, and C. Yoo, "A 1.62/2.7Gbps Clock and Data Recovery with Pattern Based Frequency Detector for DisplayPort," IEEE Transaction on Consumer Electronics, vol. 56, no. 4, pp. 2032-2036, Nov. 2010. DOI ScienceOn |
6 | J. Song, I. Jung, M. Song, Y.-H. Kwak, S. Hwang, and C. Kim, "A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiverfor DisplayPort v1.1a With Weighted Phase and Frequency Detection," IEEE Transactions on Circuits and Systems, vol. 60, no. 2, pp. 268-278, Feb. 2013. DOI ScienceOn |
7 | M. Hossain et al., "A 7.4 Gb/s 6.8 mW source synchronous receiver in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899-908, Apr. 2010. DOI ScienceOn |
8 | M. Hwang et al., "A 180-Mb/s to 3.2 Gb/s, Continuous-rate, Fast-locking CDR without Using External Reference Clock," in Proc. IEEE Asian Solid-State Circuits Conf., 2007, pp. 144-147. |
9 | J.-K. Woo, H. Lee, W.-Y Shin, H. Song, D.-K Jeong, and S. Kim, "A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter," IEEE ASSCC 2006, pp. 411-414, Nov. 2006. |
10 | W.-H Zhao, Z.-G. Wang, and E. Zhu, "A 3.125-Gb/s CMOS Word Alignment Demultiplexer for Serial Data Communications," in Proc. IEEE European Solid-State Circuits Conf., 2003, pp. 389-392. |
11 | Y. Zhen, and H. Qing-sheng, "A Comma Detection and Word Alignment Circuit for High-speed SerDes," IEEE WiCOM 2011, pp. 1-4. |
12 | R. Inti et al., "A 0.5-to-2.5 Gb/s Reference-less Half-rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Input Dutycycle Error Tolerance," IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3150-3162, Dec. 2011. DOI ScienceOn |
13 | L. Hai Qi et al., "A Low-noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and Fine Frequency Tuning," IEEE Trans. Very Large Scale Integr. Syst. , vol. 17, pp. 571-577, 2009. DOI ScienceOn |
14 | S. Zhinian et al., "A 2.4-GHz Ring-oscillator-based CMOS Frequency Synthesizer with a Fractional Divider Dual-PLL Architecture," IEEE J. Solid-State Circuits, vol. 39, pp. 452-462, 2004. DOI ScienceOn |
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