• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.194-201
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• 2015

A frequency modulated ultra-wideband (FM-UWB) transmitter with a high-robust relaxation oscillator for subcarrier generation and a dual-path Ring VCO for RF FM is proposed, featuring low power and low complexity. A prototype 3.65-4.25 GHz FM-UWB transceiver employing the presented transmitter is fabricated in $0.18{\mu}m$ CMOS for short-range wireless data transmission. Experimental results show a bit error rate (BER) of $10^{-6}$ at a data rate of 12.5 kb/s with a communication distance of 60 cm is achieved and the power dissipation of 4.3 mW for the proposed transmitter is observed from a 1.8 V supply.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.773-779
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• 2013

We propose an efficient method to measure a pulse width using multiphase clock signals generated from a ring oscillator. These clocks, which have the same frequency and are evenly spaced, give multiple rising edges within a clock cycle. Thus, it is possible to measure a pulse width more accurately than with existing single clock-based methods. The proposed method is applied to a capacitive touch switch. Experimental results show that the capacitive touch switch with the proposed method gives a 118 fF resolution, which is 6.4 times higher than that of the touch switch with a single clock-based pulse width measurement method.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.30-37
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• 2014

In this paper, the compact model for FinFET gate resistance is developed. Based on the FinFET geometry and material, the value of the gate resistance is extracted by Y-parameter analysis using 3D device simulator, Sentaurus. By dividing the gate resistance into horizontal and vertical components, the proposed gate resistance model captures the non-linear characteristics. The proposed compact model reflects the realistic gate structure which has two different materials (Tungsten, TiN) stacked. Using the proposed model, the number of fins for the minimum gate resistance can be proposed based on the variation of gate geometrical parameters. The proposed gate resistance model is implemented in BSIM-CMG. A ring-oscillator is designed, and its delay performance is compared with and without gate resistance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.453-458
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• 2010

In this work, a 18 GHz divide-by-4 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in $0.13-{\mu}m$ Si RFCMOS technology. The free-running oscillation frequency is from 4.98 to 5.22 GHz and output power is about －30 dBm, consuming 33.4 mW with a 1.5 V supply voltage. At 0 dBm input power, the locking range is 3.5 GHz(17.75~21.25 GHz) and with varactor tuning, the operating range is increased up to 5.25 GHz(16.0~21.25 GHz). The fabricated chip size is $0.76\;mm{\times}0.57\;mm$ including DC and RF pad.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Journal of IKEEE
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• v.24 no.2
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• pp.543-549
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• 2020

As the importance of security increases in various fields, research on a random number generator (RNG) used for generating an encryption key, has been actively conducted. A high-quality RNG is essential to generate a high-performance encryption key, but the initial pseudo-random number generator (PRNG) has the possibility of predicting the encryption key from the outside even though a large amount of hardware resources are required to generate a sufficiently high-performance random number. Therefore, the demand of high-quality true random number generator (TRNG) generating random number through various noises is increasing. This paper examines and compares the representative TRNG methods based on metastable-based and ring-oscillator-based TRNGs. We compare the methods how the random sources are generated in each TRNG and evaluate its performances using NIST SP 800-22 tests.

• Journal of the Korean Vacuum Society
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• v.17 no.5
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• pp.461-465
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• 2008

The phase transformation in a film influences its surrounding. Effects of the precrystallization method, which removes influences on gate oxide caused by lateral crystallization, in metal-induced unilaterally crystallized polycrystalline silicon thin-film transistor devices and circuits were studied. Device by the method was shown to have a higher current drive, compared with conventional postcrystallized device. Moreover, we studied DC bias-induced changes in the performance of ring oscillator. PMOS inverters fabricated using precrystallized silicon films have very high dynamic and stable performance, compared with inverters fabricated using postcrystallized silicon films.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.