• Title/Summary/Keyword: Ring oscillator

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The K-band Oscillator using Split Ring Resonator (Split Ring 공진기를 이용한 K-Band Oscillator)

  • Han-Kee Joo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.8 no.2
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    • pp.107-115
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    • 1997
  • In this paper, a 23 GHz push-push oscillator was designed and fabricated for 23 GHz point-to-point communication using split ring resonator. The split ring resonator was equivalent circuit and numerical method of MPIE(Mixed Potential Integral Equation). The analysis of split ring resonator which coupled between microstrip lines was carried out with transmission-mode using this results. The fabricated oscillator showed the output power of 4 dBm, the 1'st harmonic suppression of -20 dBc, the 3rd harmonic suppression of -34 dBc, a SSB phase noise of -109 dBc / Hz at 1MHz offset frequency from the carrier was achieved and 1.4 percents efficiency at 23 GHz. The experimental outputs were in good results with the theoretical and simulated results.

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Implementation of Voltage Controlled Oscillator Using Planar Structure Split Ring Resonator (SRR) (평면형 구조의 분리형 링 공진기를 이용한 전압제어 발진기 구현)

  • Kim, Gi-Rae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.7
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    • pp.1538-1543
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    • 2013
  • In this paper, a novel split ring resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator. Oscillator using proposed split ring resonator is designed, it has improved phase noise characteristics. At the fundamental frequency of 5.8GHz, 7.22dBm output power and -83.5 dBc@100kHz phase noise have been measured for oscillator with split ring resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}/4$ microstrip resonator. Next, we designed voltage controlled oscillator using proposed split ring resonator with varactor diode. The VCO has 125MHz tuning range from 5.833GHz to 5.845GHz, and phase noise characteristic is -118~-115.5 dBc/Hz@100KHz. Due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

Jitter Analysis of CMOS Ring Oscillator Due to 1/f Noise of MOSFET (MOSFET의 1/f noise에 의한 CMOS Ring Oscillator의 Jitter 분석)

  • Park Se-Hoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.8
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    • pp.1713-1718
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    • 2004
  • It has been known that 1/f noise of MOSFET is generated by the superposition of single random telelgraph signals (RTS). In this study, jitters caused by 1/f noise of MOSFET are analysed with RTS supplied to all of the nodes of the CMOS ring oscillator under investigation. Through the analysis of the variations of jitters and jitter ratios with varying values of the amplitude of RTS, it is found that the jitters and the jitter ratios are proportional to the amplitude of RTS. And the analysis of FFT of the outputs of the ring oscillator reveals that the jitters are closely related to the phase noise of the high order harmonics of the ring oscillator outputs.

The Oscillation Frequency of CML-based Multipath Ring Oscillators

  • Song, Sanquan;Kim, Byungsub;Xiong, Wei
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.671-677
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    • 2015
  • A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor ${\alpha}$, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor ${\alpha}$ an attractive option for lower power applications.

Ring Oscillator Circuit for Controlling Temperature Characteristics (온도 특성을 제어하기 위한 링 발진기 회로)

  • Choi, Jin Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.883-884
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    • 2015
  • In this paper, a ring oscillator circuit having controllable output characteristics with temperature is introduced. The ring oscillator can be used in the various system to require temperature measurement. The ring oscillator is comprised of a current source and a number of NOT gates and the bias current of the current source is controlled with temperature.

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Design of a S-band Oscillator Using Vertical Split Ring Resonator (수직 분할 링 공진기를 이용한 S-밴드 발진기 설계)

  • Lee, Ju-Heun;Hong, Min-Cheol;Oh, Jeong-Taek;Yoon, Won-Sang
    • The Journal of Korean Institute of Information Technology
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    • v.17 no.3
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    • pp.43-50
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    • 2019
  • In this paper, we propose a S-band oscillator with a reduced electrical size by applying a vertical split ring resonator(VSRR). The VSRR is a type of split ring resonator that operates as a resonator by the capacitance and inductance generated between the microstrip lines arranged on the top and bottom of the dielectric substrate and it has an advantage that the electrical size of the resonance circuit can be reduced as compared with the conventional ring resonator. In this paper, we design a VSRR operating over S-band and an oscillator using the VSRR as the resonant circuit. The proposed oscillator showed the output of 5.9dBm at 2.4HGz and showed the phase noise characteristics of -112.58dBc at 100KHz offset frequency and -117.85dBc at 1MHz offset.

UWB impulse generator using gated ring oscillator (게이티드 링 발진기를 이용한 UWB 임펄스 생성기)

  • Jang, Junyoung;Kim, Taewook
    • Journal of IKEEE
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    • v.25 no.4
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    • pp.721-727
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    • 2021
  • This paper proposes a UWB (Ultar-wideband) impulse generator using the gated ring oscillator. The oscillator and PLL circuits which generate a several GHz LO signal for the conventional architecture are replaced with the gated ring oscillator. Therefore, the system complexity is decreased. The proposed architecture controls the duty of enable signal, which is used for the head switch of ring oscillator. The control of the duty enables to tun off the oscillator during the guard interval and stop wasting the power consumption. The pulse shaping method using the counter makes the small side lobe and preserves the bandwidth regardless of the change on the center frequency. Designed UWB impulse generator could change the center frequency from 6.0 GHz to 8.8 GHz with a digital bit control, while it preserves the bandwidth as about 1.5 GHz.

CMOS Integrated Multiple-Stage Frequency Divider with Ring Oscillator for Low Power PLL

  • Ann, Sehyuk;Park, Jusang;Hwang, Inwoo;Kim, Namsoo
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.4
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    • pp.185-189
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    • 2017
  • This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadband and high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to divide the frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure the frequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of the divider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 ${\mu}m$ CMOS process. Simulation shows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for an input frequency of 1.2 GHz, with a power consumption of 30 mW.

Low-Phase Noise Oscillator Using Substrate Integrated Waveguide and Complementary Split Ring Resonator (기판 집적형 도파관(SIW)과 Complementary Split Ring Resonator(CSRR)로 구현한 저위상 잡음 발진기 설계)

  • Park, Woo-Young;Lim, Sung-Joon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.4
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    • pp.468-474
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    • 2012
  • A low phase-noise microwave oscillator is presented by a substrate integrated waveguide(SIW) loading a complementary split ring resonator(CSRR) in this paper. The unloaded $Q$-factor of the SIW cavity is increased by loading a complementary split ring resonator(CSRR) and its value exhibits 1960. It is theoretically and experimentally demonstrated that the proposed circuit generates 11.3 dBm of output power at 9.3 GHz and a phase-noise of -127.9 dBc/Hz at 1-MHz offset.

Implementation and Design of the Voltage Controlled Oscillator Using Ring type DGS Resonator (링형 DGS 공진기를 이용한 전압제어 발진기의 설계 및 구현)

  • Kim, Girae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.12
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    • pp.2589-2594
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    • 2012
  • In this paper, a novel resonator using ring type DGS is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator, and oscillator for 5.8 GHz band is designed using proposed DGS resonator. The ring type DGS resonator is composed of DGS cell etched on ground plane under $50{\Omega}$ microstrip line. At the fundamental frequency of 5.8 GHz, 7.6 dBm output power and -82.7 dBc@100kHz phase noise have been measured for oscillator with ring type DGS resonator. We designed the voltage controlled oscillator using proposed the DGS resonator with varactor diodes placed between gaps of DGS. Thus, due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.