• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.22 no.9
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• pp.896-902
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• 2012

For most applications of the vibration energy harvesting technology as in wireless sensor networks for smart buildings and plants, the evaluation of DC output performance of vibration energy harvesters is typically required. However, there is no dedicated algorithm for the evaluation. The lack of a dedicated algorithm results from difficulties in the direct incorporation of nonlinear rectifying and regulating circuitry into finite element models of piezoelectric vibration energy harvesters. In this study, we develop a dedicated algorithm and present software based on it for the evaluation of not only AC but also DC electrical quantities. Here, an equivalent electrical circuit model is employed. The COMSOL multiphysics simulation tool is adopted for extracting equivalent electrical circuit parameters of a piezoelectric vibration energy harvester and MATLAB is used to make a graphical user interface. The AC voltage and power outputs calculated by the proposed algorithm under various conditions are compared with those by a traditional finite element analysis. The DC output voltage and power through a rectifier are obtained for varying values of smoothing capacitance and external resistance.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.69-77
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• 2016

We propose nano-scale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nano-scale Cu direct bonding using CNP. Nano-scale Cu pillar easily bond with Cu electrode by re-crystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional micro-scale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with $80{\mu}m$ height is around 30 m for each pair of $10{\mu}m$ dia. electrode. Capacitance value of CNP bundle with $3{\mu}m$ length and $80{\mu}m$ height is around 0.6fF. Eye-diagram pattern shows no degradation even at 10Gbps data rate after the lamination of anisotropic conductive film.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.1
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• pp.41-46
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• 2012

Electrolytic power capacitors have been widely used in power conversion system such as inverter or UPS because of characteristics of large capacitance, high-voltage and low-cost. The electrolytic capacitor, which is most of the time affected by the aging effect, plays a very important role for the power-electronics system quality and reliability. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure. In this paper, the on-line remote diagnosis monitoring system for UPS DC link electrolytic capacitors using low-cost single-chip zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using BPF modeling of DC link ripple voltage/current. Zigbee-based hardware experimental results show that the proposed remote capacitor diagnosis monitoring system can be applied to UPS successfully.

• Current Photovoltaic Research
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• v.2 no.2
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• pp.69-72
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• 2014

We investigated current-voltage (I-V) and capacitance (C)-V characteristics of solution-processed thin film solar cells, consisting of $Cu(In,Ga)S_2$ and $CuInS_2$ stacked absorber layers. The ideality factors, extracted from the temperature-dependent I-V curves, showed that the tunneling-mediated interface recombination was dominant in the cells. Rapid increase of both series- and shunt-resistance at low temperatures would limit the performance of the cells, requiring further optimization. The C-V data revealed that the carrier concentration of the $CuInS_2$ layer was about 10 times larger than that of the $Cu(In,Ga)S_2$ layer. All these results could help us to find strategies to improve the efficiency of the solution-processed thin film solar cells.

• Journal of Electrochemical Science and Technology
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• v.7 no.2
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• pp.153-160
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• 2016

The inhibition ability of N,N-bis(2,4-dihydroxyhydroxybenzaldehyde)-1,3-Propandiimine (DHBP) as a schiff base against the corrosion of API-5L-X65 steel in 1 M HCl solution was evaluated by electrochemical impedance spectroscopy, potentiodynamic polarization and scanning electron microscopy. Electrochemical impedance studies indicated that DHBP inhibited corrosion by blocking the active corrosion sites. The inhibition efficiency increased with increasing inhibitor concentrations. EIS data was analysed to equivalent circuit model and showed that the charge transfer resistance of steel increased with increasing inhibitor concentration whilst the double layer capacitance decreased. The adsorption of this compound obeyed the Langmuir adsorption isotherm. Gibbs free energy of adsorption was calculated and indicated that adsorption occurred through physical and spontaneous process. The corrosion inhibition mechanism was studied by potential of zero charge. Polarization studies indicated that DHBP retards both the cathodic and anodic reactions through adsorption on steel surface. Scanning electron microscopy was used to study the steel surface with and without inhibitor.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.11
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• pp.471-474
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• 1997

Recently, many studies have shown clinically the detection of proximal arterial stenosis through evaluation of a Doppler waveform alternation, the so-called pulsus tardus and parvus, that often occurs distal to the stenosis. However the cause of the tardus-parvus phenomenon remains obscure. To analyze its cause, we modeled the blood-flow circuit as simple electrical circuit. This shows that pulsus tardus-parvus effect is caused as a result of high-frequency waveform component attenuation from low-pass filtering by capacitance(complience of the poststenotic vessel wall) and resistance(stenosis). As a result, the degree of pulsus tardus-parvus increased as the complience of the poststenotic segment of vessel increased, as well as increasing stenosis.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.