• Journal of Power Electronics
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• 제9권4호
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• pp.593-603
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• 2009

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.362-371
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• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Journal of Power Electronics
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• 제15권1호
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• pp.96-105
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• 2015

In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권8호
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• pp.509-513
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• 2000

This paper deals with the parallel operation of space vector PWM for large capacity inverter system. To enlarge the capacity of inverter system and to reduce the current ripples on inverter output side, two or more inverters are operated in parallel. In this paper, a new parallel operation strategy which minimizes the harmonic distortion of the output stage is described. The proposed method is developed on the basis of the space-vector PWM in order to increase the linearly controllable voltage range. With the help of the proposed voltage synthesis method, the total harmonic distortion of the output stage can be greatly reduced in compared with that of conventional method with sinusoidal PWM or that of the single inverter operation case. The experimental results with reduced scale test show the feasibility of the proposed voltage synthesis method.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1328-1336
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• 2013

Nowadays multilevel inverters are developing generally due to reduced voltage stress on power switches and low total harmonic distortion (THD) in output voltage. However, for increasing the output voltage levels the number of circuit devices are increased and it results in increasing the cost of converter. In this paper, a novel multilevel inverter is proposed. The suggested topology uses less number of power switches and related gate drive circuits to generate the same level in output voltage with comparison to traditional cascaded multilevel inverter. With the proposed topology all levels in output voltage can be realized. As an illustration, a symmetric 13-level and asymmetric 29-level proposed inverters have been simulated and implemented. The total peak inverse (PIV) and power losses of presented inverter are calculated and compared with conventional cascaded multilevel inverter. The presented analyses show that the power losses in the suggested multilevel inverter are less than the traditional inverters. Presented simulation and experimental results demonstrate the feasibility and applicability of the proposed inverter to obtain the maximum number of levels with less number of switches.

• 한국통신학회논문지
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• 제21권5호
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• pp.1325-1331
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• 1996

본 논문에서는 전류 스위칭(switched-current:SI) 시스템에서 THD(total harmonic distortion) 증가 원인인 클럭피드스루(clock feedthrough:CFT) 오차 전압을 감소시키는 새로운 전류 메모리(current-memory) 회로를 제안하였다. 제안한 전류 메모리는 CMOS 상보형의 PMOS 트랜지스터를 이용하여 CFT 오차 전압에 의한 출력 왜곡 전류를 감소시킨다. 제안한 전류 메모리 회로를 $1.2{\mu}{\textrm{m}}$ CMOS 공정을 사용하여 설계하고, 입력으로 전류 크기 $68{\mu}{\textrm{m}}$인 1MHz 정현파 신호를 인가하였다.(샘플링 주파수:20MHz) 모의 실험 결과, 기존의 전류 메모리보다 CFT 오차 전압에 의한 출력 왜곡 전류가 10배 정도 감소를 나타내었으며 신호 대 바이어스 전류비가 0.5(peak signal-to-bias current ratio:i/J)인 1KHz 신호를 인가할 경우 THD는 -57dB이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.754-755
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• 2008

This paper presents a method for reducing the Total Harmonic Distortion(THD) of line-line back_EMF of the IPMSM with distributed winding under the no-load condition. Firstly, the specific harmonic components of line-line back EMF are reduced considering with winding factor. Secondly, THD of line-line back EMF is minimized according to change of pole angle using by Space harmonic Analysis. Finally, the optimal design for minimizing the THD is conducted using response surface methodology with finite element analysis. The validity of the design method dealt with in this paper is demonstrated by comparison between the THD of optimal model and initial model.

• Journal of Power Electronics
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• 제11권4호
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• pp.490-498
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• 2011

This paper presents a novel analysis, design, and implementation of a battery charging three-phase high frequency semi-controlled power converter feasible for plug-in hybrid electric vehicles. The main advantages of the proposed topology include high efficiency; due to lower power losses and reduced number of switching elements, high output power density realization, and reduced passive component ratings proportionally to the frequency. Additional advantages also include grid economic utilization by insuring unity power factor operation under different possible conditions and robustness since short-circuit through a leg is not possible. A high but acceptable total harmonic distortion of the generator currents is introduced in the proposed topology which can be viewed as a minor disadvantage when compared to traditional boost rectifiers. A hysteresis control algorithm is proposed to achieve lower current harmonic distortion for the rectifier operation. The rectifier topology concept, the principle of operation, and control scheme are presented. Additionally, a dc-dc converter is also employed in the rectifier-battery connection. Test results on 50-kHz power converter system are presented and discussed to confirm the effectiveness of the proposed topology for PHEV applications.

• Journal of Power Electronics
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• 제10권4호
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• pp.419-427
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• 2010

A parallel control strategy in capacity proportion frequency allocation mode for shunt active power filters (APFs) is proposed to overcome some of the difficulties in high power applications. To improve the compensation accuracy and overall system stability, an improved selective harmonic current control based on multiple synchronous rotating reference coordinates is presented in a single APF unit, which approximately implements zero steady-state error compensation. The combined decoupling strategy is proposed and theoretically analyzed to simplify selective harmonic current control. Improved selective harmonic current control forms the basis for multi-APF parallel operation. Therefore, a parallel control strategy is proposed to realize a proper optimization so that the APFs with a larger capacity compensate more harmonic current and the ones with a smaller capacity compensate less harmonic current, which is very practical for accurate harmonic current compensation and stable grid operation in high power applications. This is verified by experimental results. The total harmonic distortion (THD) is reduced from 29% to 2.7% for a typical uncontrolled rectifier load with a resistor and an inductor in a laboratory platform.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.88-90
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• 2012

A study on an integrated single stage AC/DC converter is presented in this paper. The input current can be controlled by the auxiliary winding($L_{aux}$), auxiliary primary winding($N_3$), and the boost inductor($L_B$) which are designed to operate in discontinuous conduction mode(DCM) to reduced the total harmonic distortion(THD) of input current. The auxiliary primary winding($N_3$) is critically selected in order to compress the input capacitor voltage($V_{in}$) as well as to reduce the current stress of the switch(Q). Low total harmonic distortion(THD), low input voltage($V_{in}$) in universal input voltage($V_{AC}$), low current stress at the switching device and high efficiency are the main consideration keys in this design to achieve high performance system with low cost of single stage AC/DC converter. A 30W single stage AC/DC prototype converter is under study.