• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.367-369
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• 1995

An SOI LDMOS(Silicon-On-Insulator Lateral Double diffused MOSPET) with a tapered field plate is proposed and investigated in terms of the breakdown voltage and on-resistance using 2-D simulator, MEDICI. The results of conventional SOI LDMOS with a stepped field plate are reported for the comparison. Simulated breakdown voltage of the proposed LDMOS is found to be higher than that of conventional LDMOS since surface electric field can be reduced due to the field plate over the tapered oxide. On-resistance of proposed LDMOS is found to be lower than that of conventional LDMOS by 10%.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• Journal of IKEEE
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• v.18 no.2
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• pp.214-219
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• 2014

In this paper, the usage of tilt-implanted trench Schottky diode(TITSD) based on silicon carbide is proposed. A tilt-implanted trench termination technique modified for SiC is proposed as a method to keep all the potentials confined in the trench insulator when reverse blocking mode is operated. With the side wall doping concentration of $1{\times}10^{19}cm^{-3}$ nitrogen, the termination area of the TITSD is reduced without any sacrifice in breakdown voltage while potential is confined within insulator. When the trench depth is set to 11um and the width is optimized, a breakdown voltage of 2750V is obtained and termination area is 38.7% smaller than that of other devices which use guard rings for the same breakdown voltage. A Sentaurus device simulator is used to analyze the characteristics of the TITSD. The performance of the TITSD is compared to the conventional trench Schottky diode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.9-14
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• 2004

This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1080-1086
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• 2005

We have studied the Ge redistribution after dry oxidation and the oxide growth rate of $Si_{1-x}Ge_x$ epitaxial layer. Oxidation were performed at 700, 800, 900, and $1,000\;^{\circ}C$. After the oxidation, the results of RBS (Rutherford Back Scattering) & AES(Auger Electron Spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $Si_{1-x}Ge_x$ interface. It is shown that the presence of Ge at the $Si_{1-x}Ge_x$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700 and 800$^{\circ}C$, while it was decreased at both 900 and $1,000^{\circ}C$ as the Ge mole fraction was increased. The dry of idation rates were reduced for heavy Ge concentration, and large oxiidation time. In the parabolic growth region of $Si_{1-x}Ge_x$ oxidation, the parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the $1,000^{\circ}C$, AES showed that Ge peak distribution at the $Si_{1-x}Ge_x$ interface reduced by interdiffusion of silicon and germanium.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.193.2-193.2
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• 2016

We evaluate the change in defects in the oxidized SiO2 grown on 4H-SiC (0001) by plasma assisted oxidation, by comparing with that of conventional thermal oxide. In order to investigate the changes in the electronic structure and electrical characteristics of the interfacial reaction between the thin SiO2 and SiC, x-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), DFT calculation and electrical measurements were carried out. We observed that the direct plasma oxide grown at the room temperature and rapid processing time (300 s) has enhanced electrical characteristics (frequency dispersion, hysteresis and interface trap density) than conventional thermal oxide and suppressed interfacial defect state. The decrease in defect state in conduction band edge and stress-induced leakage current (SILC) clearly indicate that plasma oxidation process improves SiO2 quality due to the reduced transition layer and energetically most stable interfacial state between SiO2/SiC controlled by the interstitial C.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Journal of the Korea Institute of Building Construction
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• v.18 no.5
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• pp.419-427
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• 2018

The purpose of this study is to recycle steel slag generated from the iron producing process and to use steel slag as a construction material which is currently landfilled Steel slag is subjected to aging treatment due to the problem of expansion and collapse when it reacts with water. The Slag Atomizing Technology (SAT) method developed to solve these problems of expanding collapse of steel slag. In this study, experimental study on the emergency repair mortar using the reducing slag, electric arc furnace slag and silicon manganese slag manufactured by the SAT method is Reduced slag was shown an accelerated hydration when it was replaced with rapidly-setting cement, and the rate of substitution was equivalent to 15%. It is shown that the electric furnace oxide slag is equivalent to 100% of the natural aggregate, and it can be replaced by 15-30% when the silicon manganic slag is substituted for the electric furnace oxide slag. With the above formulation, it was possible to design the rapidly repair mortar for road use. These recycling slags can contribute on achieving sustainability of construction industry by reducing the use of cement and natural aggregates and by reducing the generation of carbon dioxide and recycling waste slag.

• Journal of the Korean Ceramic Society
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• v.39 no.4
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• pp.394-400
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• 2002

Tin oxide thin films doped with silicon as anodes for lithium secondary battery were fabricated by R. F. magnetron sputtering technique. The electrochemical results for lithium secondary battery anodes showed that addition of silicon decreases the oxidic state of tin, and, hence, reduced the irreversible capacity during the first discharge/charge cycle. The (110),(101),(211) planes were grown with increasing substrate temperatures. The reversible capacity of thin films fabricated in conditions of $300^{\circ}C$ substrate temperature and 7:3 $Ar:O_2$ ratio was 700 mAh/g.