Browse > Article

Reduction of short channel Effects in Ground Plane SOI MOSFET′s  

Jean-Pierre Colinge (Dept. of ECE, University of California)
Publication Information
Abstract
This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices
Keywords
SOI technology; MOSFET; Short Channel Effect; Ground Plane SOI MOSFET;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Jean-Pierre Colinge, Silicon-on-Ins ulator Technology: Materials to VLSI, 2nd edition, Na, Kluwer, 1997
2 H.-S.P. Wong, K.K. Chan,Y.Taur, 'Self-Aligned(Top and bottom) Double-Gate MOSFET with a 5mm thick silicon channel', Tech. Digest of IEDM, pp. 427-430, 1997   DOI
3 H.Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, 'High performance CMOS Surrounding Gate Transistor (SGT) for ultra high density LSIs,' Tech. Digest of IEDM, pp. 222-225, 1988   DOI
4 D. Hisamoto, T. Kaga, Y. Kawamoto, E.Takeda, 'A fully depleted Lean-channel Transistor(DELTA) -A novel vertical ultrathin SOI MOSFET,' Tech. Digest of IEDM, pp. 833-836, 1989   DOI
5 F.-Lyang, H.-Y.Chen, F-C,Chen, C.-C.Huang, C.-Y.Chang, H-k.Chiu, C-C.Lee, C.-C.Chen, H.-T.Huang, C.-J.Chen, H.-J.Tao, Y.-C.Yeo, M-S.Liang, and C.Hu, '25nm CMOS Omega FETs.', Tech. Digest of IEDM, pp. 255-258, 2002   DOI
6 J.P. Colinge, M.H Gao, A. Romano-Rodriguez, H Maes, and e. Claeys, 'Silicon-On-Insulator Gate-Ail-Around Device,' Tech. Digest of IEDM, pp. 595-598, 1990   DOI
7 X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.K. Choi, K. Asano, V. Subramanian, T.J. King, J. Bokor, and C. Hu, 'Sub 50nrn FinFET: PMOS,' Tech. Digest. of IEDM, pp. 67-70, 1999   DOI
8 J.T Park, J.P. Colinge, and C.H. Diaz, 'Pi-Gate SOI MOSFET,' IEEE Electron Device Letter, vol. 22, No.8, pp. 405-406, 2001   DOI   ScienceOn
9 M.Horinchi, T.Teshima, K.Tokurnasu, and K.Yamaguchi, 'High Current Small-Parasitic-Capacita nee MOSFET on a Poly-Si Interlayered(PSI:4) SOI wafer.' IEEE Trans. Electron Devices, vol.45 no.5, pp. 1111-1115, 1998   DOI   ScienceOn
10 W.xiong, K.Ramkumar, S.J. Jang, J.T. Park, and J.P. Colinge,' Self-Aligned Ground-Plane FDSOI MOSFET.' Proc. of SOI/IEEE, pp. 23-24, 2002   DOI
11 T. Ernst, and S. Cristoloveanu, 'Buried Oxide Fringing Capacitance : A new Physical Model and its Implication on SOI Device Scaling and Arch itecture. 'Proc. of SOI/IEEE, pp. 38-39, 1993, pp. 345-357, June 1998   DOI