• Title/Summary/Keyword: RTA process

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A facile synthesis of transfer-free graphene by Ni-C co-deposition

  • An, Sehoon;Lee, Geun-Hyuk;Jang, Seong Woo;Hwang, Sehoon;Yoon, Jung Hyeon;Lim, Sang-Ho;Han, Seunghee
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.129-129
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    • 2016
  • Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.

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A 45GHz $f_{T}\;and\;50GHz\;f_{max}$ SiGe BiCMOS Technology Development for Wireless Communication ICs (무선통신소자제작을 위한 45GHz $f_{T}$ 및 50GHZz $f_{max}$ SiGe BiCMOS 개발)

  • Hwang Seok-Hee;Cho Dae-Hyung;Park Kang-Wook;Yi Sang-Don;Kim Nam-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.9 s.339
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    • pp.1-8
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    • 2005
  • A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

Graphene Synthesis by Low Temperature Chemical Vapor Deposition and Rapid Thermal Anneal (저온 화학기상증착법 및 급속가열 공정을 이용한 그래핀의 합성)

  • Lim, Sung-Kyu;Mun, Jeong-Hun;Lee, Hi-Deok;Yoo, Jung-Ho;Yang, Jun-Mo;Wang, Jin-Suk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.12
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    • pp.1095-1099
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    • 2009
  • As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.

Electrical Characteristics of Ti Self-Aligned Silicide Contact (Ti Self-Aligned Silicide를 이용한 Contact에서의 전기적 특성)

  • 이철진;허윤종;성영권
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.41 no.2
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    • pp.170-177
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    • 1992
  • Contact resistance and contact leakage current of the Al/TiSiS12T/Si system are investigated for NS0+T and PS0+T junctions. SALICIDE (Self Aligned Silicide) process was used to make the Al/TiSiS12T/Si system. Titanium disilicide is one of the most common silicides because of its thermal stability, ability to form selective formation and low resistivity. In this paper, RTA temperature effect and Junction implant dose effect were evaluated to characterize contact resistance and contact leakage current. The TiSiS12T contact resistance to NS0+T silicon is lower than that to PS0+T silicon, and TiSiS12T of contact leakage current to NS0+T silicon is lower than that to PS0+T silicon. Contact resistance and contact leakage current of the Al/TiSiS12T/Si system by this method were possible for VLSI application.

A Study of low cost and high efficiency Solar Cell using SOD(spin on doping) (SOD(Spin On Doping)법을 이용한 저가 고효율 태양전지에 관한 연구)

  • Park, Sung-Hyun;Kim, Kyoung-Hae;Mon, Sang-Il;Kim, Dae-Won;Yi, Jun-Sin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07b
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    • pp.1054-1056
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    • 2002
  • High temperature Kermal diffusion from $POCl_3$ source usually used for conventional process through put of a cell manufacturing line and potentially reduce cell efficiency through bulk like time degradation. To fabricate high efficiency solar cells with minimal thermal processing, spin-on-doping(SOD) technique can be employed to emitter diffusion of a silicon solar cell. A technique is presented to emitter doping of a mono-crystalline solar cell using spin-on doping (SOD). Moreover it is shown that the sheet resistance variation with RTA temperature and time fer mono-crystalline and multi-crystalline silicon samples. This novel SOD technique was successfully used to produces 11.3% efficiency l04mm by 104mm size mono-crystalline silicon solar cells.

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Rapid Thermal Annealing of Silicon on Insulator (SOI) with a W-Halogen Lamp (텅스텐 할로겐 램프에 의한 절연층 상의 실리콘)

  • 김춘근;김용태;민석기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.950-958
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    • 1988
  • We have implemented a RTA system using W-halogen lamps and tried to recrystallize the phosphorus ion implanted amorphous silicon on insultor (SOI) taking advantages of seeding window. The purpose of this study is to investigate the possibility of a typical crystalline orientation occurred during the solidifying process of molten amorphous silicon layer. Experimental results show that several twin boundaries are found on the seeding window region after annealing for 15 sec at 1040\ulcorner. These twin boundaries represent that the recrystallization is partialy possible and when the annealing is done at 1150\ulcorner, (100) etch pits with <110> facets are found on the solidified amorphous silicon layer. Consequently, Hall mobility of recrystallized silicon film is measured and the thermal behavior of grain boundary is also observed by SEM.

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Fabrication and Characterization of InP JFET's for OEIC's (광전자집적회로를 위한 InP JFET의 제작 및 특성 분석)

  • 박철우;정창오;김성준
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.10
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    • pp.29-34
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    • 1992
  • JFET's with gate lengths ranging from 1$\mu$m to 8.3$\mu$m are successfully fabricated on InP substrate where the long haul (1.3$\mu$m~8.3$\mu$m) OEIC's(OptoElectronic Integrated Circuits) have been made. The pn junction of InP JFET's is made by co-implantation and RTA process. JFET's have etched-mesa-gate structure and the maximum gm larger than 90mS/mm was measured and this is the highest record in JFET's of such structure without S/D n$^{+}$ ion implantation. To maintain maximum g$_m$ should be well controlled the overetch of n-layer which inevitably occurs during etching off the unused p-layer. The I-V characteristic is checked during p-layer etch, for this purpose. A dc voltage gain of 11 is obtained from a preamplifier circuit thus fabricated.

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The Fabrication of Ferroelectric PZT thin films by Sol-Gel Processing (졸-겔법에 의한 강유전성 PZT박막의 제작)

  • Lee, Byoung-Soo;Lee, Duch-Chool
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.51 no.2
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    • pp.77-81
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    • 2002
  • In this study, PZT thin films were fabricated using sol-gel processing onto Si/$SiO_2$/Ti/Pt substrates. PZT sol with different Zr/Ti ratio(20/80, 30/70, 40/60, 52/48) were prepared, respectively. The films were fabricated by using the spin-coating method on substrates. The films were heat treated at $450^{\circ}C$, $650^{\circ}C$ by rapid thermal annealing(RTA). The preferred orientation of the PZT thin films were observed by X-ray diffraction(XRD), and Scanning electron microscopy(SEM). All of the resulting PZT thin films were crystallized with perovskite phase. The fine crystallinity of the films were fabricated. Also, we found that the ferroelectric properties from the dielectric constant of the PZT thin films were over 600 degrees, P-E hysteresis constant. And the leakage current densities of films were lower than $10^{-8}A/cm^2$. It is concluded that the PZT thin films by sol-gel process to be convinced of application for ferroelectric memory device.

Fabrication and Characterization of GaAs/AlGaAs HEMT Device (GaAs/AlGaAs HEMT소자의 제작 및 특성)

  • 이진희;윤형섭;강석봉;오응기;이해권;이재진;최상수;박철순;박형무
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.9
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    • pp.114-120
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    • 1994
  • We have been successfully fabricated the low nois HEMT device with AlGaAs and GaAs structure. The epitazial layer with n-type AlgaAs and undoped GaAs was grown by molecular beam epitaxy(MBE) system. Ohmic resistivity of the ource and drain contact is below 5${\times}10^{6}{\Omega}{\cdot}cm^{2}$ by the rapid thermal annealing (RTA) process. The ideality factor of the Schottky gate is below 1.6 and the gate material was Ti/Pt/Au. The HEMTs with 0.25$\mu$m-long and 200$\mu$m-wide gates have exhibited a noise figure of 0.65dB with associated gain of 9dB at 12GHz, and a transconductance of 208mS/mm.

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Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices

  • Choi, Woo-Young;Lee, Jong-Duk;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.1
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    • pp.43-51
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    • 2006
  • 80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.