• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.67-75
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• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1098-1103
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• 2013

A low-noise amplifier(LNA) using series RLC matching network and resistive feedback at 8 GHz is presented. Inductive degeneration is used for the input matching with which the proposed LNA shows quite a wide bandwidth in terms of $S_{21}$. An equivalent circuit model is deduced for input matching by conversion from parallel circuit to series resonant circuit. By exploiting the resistive feedback and series RLC input matching, fully integrated LNA achieves maximum $S_{21}$ of 8.5 dB(peak to -3 dB bandwidth is about 3.5 GHz) noise figure of 5.9 dB, and IIP3 of 1.6 dBm while consuming 7 mA from 1.2 V supply.

• 전기의세계
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• v.22 no.2
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• pp.40-44
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• 1973

A method for obtaining state equation for nonlinear time-varying RLC networks is presented. The nonlinear time-varying RLC elements are decomposed by using Murata method to formulate nonlinear state equation. A nonlinear time-varying RLC network containing twin tunnel diode is solved as an example. In consequence of solving the examjple, simple methods are presented for revising the original network model so that the formulation of state equation is simplified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.20-28
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• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.13-26
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• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.183-185
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• 2002

This paper proposes the test method for the testing of a RLC parallel circuit on the electronic circuit board. This method utilizes a guarding circuit and a phase detection circuit. The guarding circuit separates electrically the tested device or circuit from printed circuit board. Phase detector estimates the phase difference from two signals, voltage and current. This method computes R. L and C value from phase difference($\theta$) and impedance value(Z) obtained by enforcing two other frequence stimulus under the guarding state.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.29-37
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• 2006

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.7
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• pp.733-740
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• 2013

The high-velocity electromagnetic forming (EMF) process is based on the Lorentz force and the energy of the magnetic field. The advantages of EMF include improved formability, wrinkle reduction, and non-contact forming. In this study, numerical simulations were conducted to determine the practical parameters for the EMF process. A 2-D axis-symmetric electromagnetic model was used, based on a spiral-type forming coil. In the numerical simulation, an RLC circuit was coupled to the spiral coil to measure various design parameters, such as the system input current and the electromagnetic force. The simulation results show that even though the input peak current levels were at the same level in each case, the forming condition varied due to differences in the frequency of the input current. Thus, the electromagnetic forming force was affected by the input current frequency, which in turn, determined the magnitude of the current density and the magnetic flux density.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.8
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• pp.475-481
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• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.6
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• pp.81-86
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• 2006

Routing signal lines in PCB, line shapes would be straight or bent. time-domain and frequency-domain evaluation of the signal property and interference are archived by precise Modeling of differential signal line. Some of CAD tools can extract equivalent circuit model parameters. but it takes a long time and heavy loads. This paper introduces a basic RLC equivalent circuit model parameter extraction technique for bent differential structures using genetic algorithm by this technique, we can model equivalent circuit of bent differential structures more faster.