• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.818-823
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• 2003

본 논문에서는 입력 매칭(input matching) BIST(Built-In Self-Test) 회로를 이용한 RF font end의 새로운 결함 검사방법을 제안한다. BIST 회로를 가진 RF front end는 1.8GHz LNA(Low Noise Amplifier: 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 0.25$\mu\textrm{m}$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함 및 parametric 변동을 가진 RF front end와 결함을 갖지 않은 RF front end를 판별하기 위해 RF front end의 입력 전압 특성을 조사하였다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전자계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 RF front end가 차지하는 전체면적의 약 10%에 불과하다. 본 논문에서 제안하는 검사기술을 이용하여 시뮬레이션해 본 결과 catastrophic 결함에 대해서는 100%, parametric 변동에 대해서는 약 79%의 결함을 검출할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.273-278
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• 2011

This paper has proposed a dual-band transmitter RF Front-end for IMT-Advanced systems which has been implemented in a 0.13-${\mu}m$ CMOS technology. The proposed dual-band transmitter RF Front-End covers 2300~2700 MHz, 3300~3800 MHz frequency ranges which support 802.11, Mobile WiMAX, and IMT-Advanced system. The proposed dual-band transmitter RF Front-End consumes 45 mA from a 1.2 V supply voltage. The performances of the transmitter RF Front-End are verified through post-layout simulations. The simulation results show a +0 dBm output power at 2 GHz band, and +1.3 dBm output power at 3 GHz band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.449-455
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• 2004

This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.183-189
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• 2009

In this paper, we propose RF front-end architecture using hybrid conversion method to receive broadband signal. The validity is verified by design, fabrication and experiment. The proposed RF front-end architecture due to up-conversion block improves the deficiency of performance deterioration to be generated through harmonic signal and image signal conversion in the conventional RF front-end, and improves the deficiency of the complexity that is from to adopt a multiple local oscillators for the generation of wideband LO signal in the conventional RF front-end by applying the principle that tuning bandwidth is multiplied at sub-harmonic mixer. Manufactured circuits satisfy the deduced design specification and target standard with gain above 80 dB, noise figure below 6.0 dB and IIP3 performance above -5.0 dBm for the condition of the minimum gain in RF front-end.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.11
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• pp.61-68
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• 2008

In this paper, we propose a RF front-end developments for vehicle UWB radar systems. UWB systems have a very narrow pulse width that is below 1ns. Therefore, UWB is designed to have broadband quality of low power several GHz and must coexist with the radio communication system. UWB's advantages include high channel capacity and data rate, because precise resolution for multi-path can easily position estimate and Rake receiver. Also, UWB has low interference because it displays broadband quality of low power. Positioning is made possible by short range accuracy, which can reduce the expense of system design. An RF front-end module is designed using the DCR(Direct ConveRsion) method and is composed in RF for vehicles at a low-cost.

• ETRI Journal
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• v.33 no.6
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• pp.969-972
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• 2011

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-${\mu}m$ CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.59-64
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• 2011

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

• Journal of Advanced Navigation Technology
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• v.12 no.6
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• pp.604-610
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• 2008

A 2.4 GHz CMOS RF front-end using for ZigBee application is described The front-end consists of a low noise amplifier and a down-mixer and uses a 2 MHz IF frequency. A common source with resistive feedback and an inductive degeneration are adopted for a low noise amplifier, and a 20 dB gain control step is digitally controlled. A passive mixer for low current consumption is employed. The RF front-end is implemented in 0.18 ${\mu}m$IP6M CMOS process. The measured performance is 4.44 dB NF and -6.5 dBm IIP3 while consuming 3.28 mA current from a 1.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1009-1014
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• 2012

This paper has proposed a 2,500 MHz ~ 2,570 MHz 0.13-${\mu}m$ CMOS RF front-end transmitter for LTE-Advanced systems. The proposed RF front-end transmitter is composed of a quadrature up-conversion mixer and a driver amplifier. The measurement results show the maximum output power level is +6 dBm and the suppression ratio for the image sideband and LO leakage are better than -40 dBc respectively. The fabricated chip consumes 36 mA from a 1.2 V supply voltage.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.421-422
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• 2008

In this paper, CMOS RF front-end circuits for an L1/L5 dual-band global positioning system (GPS)/Galileo receiver are designed in $0.13\;{\mu}m$ CMOS technology. The RF front-end circuits are composed of an RF single-to-differential low noise amplifier, an RF polyphase filter, two down-conversion mixers, two transimpedance amplifiers, a IF polyphase filter, four de-coupling capacitors. The CMOS RF front-end circuits provide gains of 43 dB and 44 dB, noise figures of 4 dB and 3 dB and consume 3.6 mW and 4.8 mW from 1.2 V supply voltage for L1 and L5, respectively.