JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 ㎛ CMOS

  • Choi, Jae-Yi (School of Electrical Engineering, Pusan National University) ;
  • Seo, Shin-Hyouk (School of Electrical Engineering, Pusan National University) ;
  • Moon, Hyun-Won (Samsung Electronics) ;
  • Nam, Il-Ku (School of Electrical Engineering, Pusan National University)
  • Received : 2010.12.02
  • Accepted : 2011.02.17
  • Published : 2011.03.31
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Abstract

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

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References

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