• Proceedings of the Korean Vacuum Society Conference
• /
• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
• /
• pp.382-383
• /
• 2013

Gate-controlled spin-orbit interaction parameter is a key factor for developing spin-Field Effect Transistor (Spin-FET) in a quantum well structure because the strength of the spin-orbit interaction parameter decides the spin precession angle [1]. Many researches show the control of spin-orbit interaction parameter in n-type quantum channels, however, for the complementary logic device p-type quantum channel should be also necessary. We have calculated the spin-orbit interaction parameter and the effective mass using the Shubnikov-de Haas (SdH) oscillation measurement in a GaSb two-dimensional hole gas (2DHG) structure as shown in Fig 1. The inset illustrates the device geometry. The spin-orbit interaction parameter of $1.71{\times}10^{11}$ eVm and effective mass of 0.98 $m^0$ are obtained at T=1.8 K, respectively. Fig. 2 shows the gate dependence of the spin-orbit interaction parameter and the hole concentration at 1.8 K, which indicates the spin-orbit interaction parameter increases with the carrier concentration in p-type channel. On the order hand, opposite gate dependence was found in n-type channel [1,2]. Therefore, the combined device of p- and n-type channel spin transistor would be a good candidate for the complimentary logic device.

• Journal of the Optical Society of Korea
• /
• 제18권1호
• /
• pp.65-70
• /
• 2014

This paper presents the simulation and design of an all-optical subtractor using a quantum-dot semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA MZI) structure consisting of two cascaded switches, the first of which produces the differential bit. Then the second switch produces the borrow bit by using the output of the first switch and the subtrahend data stream. Simulation results were obtained by solving the rate equations of the QD-SOA. The effects of QD-SOA length, peak power and current density have been investigated. The designed gate can operate at speeds of over 250 Gb/s. The simulation results demonstrate a high extinction ratio and a clear and wide-opening eye diagram.

• Korean Journal of Optics and Photonics
• /
• 제4권3호
• /
• pp.294-300
• /
• 1993

Monolithic NOR and INVERTER active optical logic devices inte- grated with surface-emitting microlasers, heterojunction photo- transistors(HPT) in parallel and resistors in series are characterized. The differential quantum efficiency of the typical AlGaAs superlattice microlaser integrated in the active optical logic devices is 15%. Current gain of the HPT is 57, when emitter-collector voltage and input optical power are 4 V and $50{\mu}W$, respectively. $57{\mu}W$ of output power from the active optical logic device decreases to zero when $47{\mu}W$ of input optical power is incident on the HPT part of the active logic device.

• ETRI Journal
• /
• 제36권1호
• /
• pp.89-98
• /
• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• Journal of Advanced Navigation Technology
• /
• 제20권6호
• /
• pp.631-637
• /
• 2016

Quantum cellular automata (QCA) are one of the alternative technologies that can overcome the limits of complementary metal-oxide-semiconductor (CMOS) scaling. It consists of nano-scale cells and demands very low power consumption. Various circuits on QCA have been researched until these days, and in the middle of the researches, exclusive-OR (XOR) gates are used as error detection and recover. Typical XOR logic gates have a lack of scalable, many clock zones and crossover designs so that they are difficult to implement. In order to overcome these disadvantages, this paper proposes XOR design using majority gate reduced clock zone. The proposed design is compared and analysed to previous designs and is verified the performance.

• The Journal of the Korea institute of electronic communication sciences
• /
• 제11권1호
• /
• pp.29-36
• /
• 2016

Recently a new class of quantum gate called $NCV-{\mid}v_1$ > library with low cost realizable potentialities is being watched with keen interest. The $NCV-{\mid}v_1$ > MCT gate is composed of AND cascaded-$CV-{\mid}v_1$ > gates to control the target qudit and its adjoint gates to erase junk ones. This paper presents a new symmetrical duality library named $NCV^{\dag}-{\mid}v_1$ > library corresponding to $NCV-{\mid}v_1$ > library. The new $NCV^{\dag}-{\mid}v_1$ > library can be operated on OR logic under certain conditions. By using both the $NCV-{\mid}v_1$ > and $NCV^{\dag}-{\mid}v_1$ > libraries it is possible to realize MPMCT gates, SOP and POS type synthesis of quantum logic circuits with extremely low cost, and expect dual gate property caused by different operational attributes with respect to forward and backward operations.

• Progress in Superconductivity
• /
• 제8권2호
• /
• pp.181-185
• /
• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• Korean Journal of Optics and Photonics
• /
• 제17권6호
• /
• pp.564-568
• /
• 2006

Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

• 한국초전도학회:학술대회논문집
• /
• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
• /
• pp.238-241
• /
• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

• Progress in Superconductivity and Cryogenics
• /
• 제4권1호
• /
• pp.35-39
• /
• 2002

We have simulated and laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. SFQ AND gate circuit is a combination of two D Flip-Flop. D Flip-Flop and dc SQUID are the similar shape form the fact that it has the loop inductor and two Josephson junction We obtained perating margins and accomplished layout of the AND gate. We got the margin of $\pm$38%. over. After layout, we drew mask for fabrication of SFQ AND sate. This mask was included AND gate, dcsfq, sfqdc, rs flip-flop and jtl.