• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1899-1909
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• 2007

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8B
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• pp.777-785
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• 2009

In recent wireless sensor networks, stationary nodes and mobile nodes co-exist to provide a diverse service. However, because there are multiple mobile nodes located in the wireless sensor network, there is a potential for the instability due to the frequent network reconfiguration and the traffic caused by densely concentration of mobile nodes while mobile nodes are switching locations. In order to solve this problem, we propose the pumping node architecture to solve this traffic congestion problem due to the crowds of mobile nodes. The pumping node can be reduced heavy traffic by pumping through the backbone network caused by the densely concentration of the mobile nodes. As a result, the architecture reduces the traffic in the sensor network with high reliability.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.776-780
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• 2007

In this paper, the charge pump circuit of a VPP generator for a low voltage DRAM is newly proposed. The proposed charge pump is a 2-stage cross coupled charge pump circuit. The charge transfer efficiency is improved, and Distributed Clock Inverter is located in each charge pump stage to reduce clock period so that the pumping current is increased. In addition, the precharge circuit is located at Gate node of charge transfer transistor to solve the problem which is that the Gate node is maintained high voltage because the boosted charge can't discharge, so device reliability is decreased. The simulation result is that pumping current, pumping efficiency and power efficiency is improved. The layout of the proposed VPP generator is designed using $0.18{\mu}m$ Triple-Well process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1266-1274
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• 2006

A non-overlap boosted-clock charge pump(NBCCP) with internal pumping capacitor, an advantageous circuit from a minimizing point of TFT-LCD driver IC module, is proposed in this paper. By using the non-overlap boosted-clock swinging in 2VDC voltage, the number of pumping stages is reduced to half and a back current of pumping charge from charge pumping node to input stage is also prevented compared with conventional cross-coupled charge pump with internal pumping capacitor. As a result, pumping current of the proposed NBCCP circuit is increased more than conventional cross-coupled charge pump, and a layout area is decreased. A proposed DC-DC converter for TFT-LCD driver IC is designed with $0.18{\mu}m$ triple-well CMOS process and a test chip is in the marking.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.312-320
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• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• Journal of Korean Society for Geospatial Information Science
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• v.4 no.2 s.8
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• pp.55-61
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• 1996

The objective of this paper is to show an optimal design model for branched water supply system which also can find the optimal location of pumping stations using linear programming. GIS is utilized in this model to better handle the data and the results front the optimization. The developed model considers hydraulic influences of some appurtenances such as supply tunnels and a filtration plant The model also considers tunnel construction cost which should be treated differently from pipe construction cost Different from other models presently available, the model guarantees a nonnegative pressure at every junction node in the system. The objective function includes annual operation cost (electricity rate) ill addition to initial construction cost, thus producing a more reasonable decision. The model selects the optimal diameter not in the form of continuous number but in the form of commercial discrete diameter (pipe size) using the pipe lengths as decision variables instead of pipe diameters. The model not only determines the optimal pumping head for each pumping station but also finds the optimal location and number of pumping stations. GIS is used to handle hydraulic and budgetary data automatically and to visualize the results for the of optimal design of the system. The model has been applied to an existing water supply system. 'The results show that the optimization model with the aid of GIS is helpful in the decision-nulling process for the design of more economical systems, and can be dot into practice successfully.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.6
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• pp.558-569
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• 2017

In this paper, a 256Kb EEPROM IP aimed at battery applications using a single supply of 1.5V which is embedded into an MCU is designed. In the conventional cross-coupled VPP (boosted voltage) charge pump using a body-potential biasing circuit, cross-coupled PMOS devices of 5V in it can be broken by the junction or gate oxide breakdown due to a high voltage of 8.53V applied to them in exiting the program or erase mode. Since each pumping node is precharged to the input voltage of the pumping stage at the same time that the output node is precharged to VDD in the cross-coupled charge pump, a high voltage of above 5.5V is prevented from being applied to them and thus the breakdown does not occur. Also, all erase, even program, odd program, and all program modes are supported to reduce the times of erasing and programming 256 kilo bits of cells. Furthermore, disturbance test time is also reduced since disturbance is applied to all the 256 kilo bits of EEPROM cells at once in the cell disturb test modes to reduce the cell disturbance testing time. Lastly, a CG driver with a short disable time to meet the cycle time of 40ns in the erase-verify-read mode is newly proposed.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.9 no.3
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• pp.97-106
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• 1989

This paper is on the modeling of two-dimensional groundwater flow, which is the first step of the development of Dynamic System Model for groundwater flow and pollutant transport in subsurface porous media. The particular features of the model are its versatility and flexibility to deal with as many real-world problems as possible. Points as well as distributed sources/sinks are included to represent recharges/pumping and rainfall infiltrations. All sources/sinks can be transient or steady state. Prescribed hydraulic head on the Dirichlet boundaries and fluxes on Neumann or Cauchy boundaries can be time-dependent or constant. Sources/sinks strength over each element and node, hydraulic head at each Dirichlet boundary node and flux at each boundary segment can vary independently of each other. Either completely confined or completely unconfined aquifers, or partially confined and partially unconfined aquifers can be dealt with effectively. Discretization of a compound region with very irregular curved boundaries is made easy by including both quadrilateral and triangular elements in the formulation. Large-field problems can be solved efficiently by including a pointwise iterative solution strategy as an optional alternative to the direct elimination solution methed for the matrix equation approximating the partial differential equation of groundwater flow. The model also includes transient flow through confining leaky aquifers lying above and/or below the aquifer of interest. The model is verified against three simple cases to which analytical solutions are available. The groundwater flow model shall be combined with the model of pollutant transport in subsurface porous media. Then the combined model, with the applications of the Eigenvalue technique and the Dynamic system theory, shall be improved to the Dynamic System Model which can simulate the real groundwater flow and the pollutant transport accurately and effectively for the analyses and predictions.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.