• Journal of the Korean Ceramic Society
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• v.54 no.6
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• pp.506-510
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• 2017

One of the characteristics of polycrystalline graphene that determines its material properties is grain size. Mechanical properties such as Young's modulus, yield strain and tensile strength depend on the grain size and show a reverse Hall-Petch effect at small grain size limit for some properties under certain conditions. While there is agreement on the grain size effect for Young's modulus and yield strain, certain MD simulations have led to disagreement for tensile strength. Song et al. showed a decreasing behavior for tensile strength, that is, a pseudo Hall-Petch effect for the small grain size domain up to 5 nm. On the other hand, Sha et al. showed an increasing behavior, a reverse Hall-Petch effect, for grain size domain up to 10 nm. Mortazavi et al. also showed results similar to those of Sha et al. We suspect that the main difference of these two inconsistent results is due to the different modeling. The modeling of polycrystalline graphene with regular size and (hexagonal) shape shows the pseudo Hall-Petch effect, while the modeling with random size and shape shows the reverse Hall-Petch effect. Therefore, this study is conducted to confirm that different modeling is the main reason for the different behavior of tensile strength of the polycrystalline structures. We conducted MD simulations with models derived from the Voronoi tessellation for two types of grain size distributions. One type is grains of relatively similar sizes; the other is grains of random sizes. We found that the pseudo Hall-Petch effect and the reverse Hall-Petch effect of tensile strength were consistently shown for the two different models. We suspect that this result comes from the different crack paths, which are related to the grain patterns in the models.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.6
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• pp.403-408
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• 2005

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random This paper proposes and presents a new efficient network architecture for Reflective Memory System (RMS). A time to copy shared-data among nodes effects critically on the entire performance of the RMS. In this paper, the recent researches about the RMS are investigated and compared. The device named Topology Conversion Switch(TCS) is introduced to realize the proposed network architecture. One of the RMS based industrial control networks, Ethernet based Real-time Control Network (ERCnet), is adopted to evaluate the performance of the proposed network architecture for RMS.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Fibers and Polymers
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• v.5 no.3
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• pp.245-251
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• 2004

Poly(trimethylene terephthalate-co-trimethylene 2,6-naphthalate)s (P(TT-co-TN)s) with various copolymer composition were synthesized, and their chain structure, thermal property and crystalline structure were investigated by using $^1$H-NMR spectroscopy, differential scanning calorimetry (DSC) and wide-angle X-ray diffraction (WAXD), respectively. It was found from sequence analysis that all the P(TT-co-TN) copolymers synthesized have a statistical random distribution of TT and TN units. It was also observed from DSC thermograms that the glass transition temperature increases linearly with increasing the TN comonomer content, whereas the melting temperature of copolymer decreases with increasing the corresponding comonomer content in respective PTT- and PTN-based copolymer, showing pseudo-eutectic melting behavior. All the samples melt-crystallized isothermally except for P(TT-co-66 mol % TN) exhibit multiple melting endotherms and clear X-ray diffraction patterns. The multiple melting behavior originates from the dual lamellar population and/or the melting-recrystallization-remelting. The X-ray diffraction patterns are largely divided into two classes depending on the copolymer composition, i.e., PTT and PTN $\beta$-form diffraction patterns, without exhibiting cocrystallization.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.594-607
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• 2013

A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.25-30
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• 2004

Linear cellular automata(CA) which generate maximum-length cycles, have wide applications in generation of pseudo-random patterns, signature analysis, cryptography and error correcting codes etc. Linear CA whose characteristic polynomial is primitive has been studied. In this paper Ive propose a effective method for generation of a variety of maximum-length CA(MLCA). And we show that the complemented CA's derived from a linear MLCA are all MLCA. Also we analyze the Properties of complemented MLCA. And we prove that the number of n-cell MLCA is ${\phi}(2^{n}-1)2^{n+1}$/n.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1105-1112
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• 2020

One-dimensional 3-neighborhood Cellular Automata (CA)-based pseudo-random number generators are widely applied in generating test patterns to evaluate system performance and generating key sequence generators in cryptographic systems. In this paper, in order to design a CA-based key sequence generator that can generate more complex and confusing sequences, we study a one-dimensional symmetric 5-neighborhood CA that expands to five neighbors affecting the state transition of each cell. In particular, we propose an n-cell one-dimensional symmetric 5-neighborhood CA synthesis algorithm using the algebraic method that uses the Krylov matrix and the one-dimensional 90/150 CA synthesis algorithm proposed by Cho et al. [6].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.