• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.191-193
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• 1989

This paper presents a optimal Var allocation algorithm for minimizing power loss and improving voltage profile in a given system. In this paper, nodal input data is considered as Gaussian distribution with their mean value and their variance. A stochastic Linear Programming technique based on chance constrained method is applied to solve the probabilistic constraint. The test result in IEEE-14 Bus model system showes that the voltage distribution of load buses is improved and the power loss is more reduced than before Var allocation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.863-865
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• 1988

This paper presents a optimal Var allocation algorithm for minimizing transmission line losses and improving voltage profile in a given system. In this paper, nodal input data is considered as Gaussian distribution with their mean value and their variance. A Stocastic Linear programming technique based on chance constrained method is applied, to solve the var allocation problem with probabilistic constraint. The test result in 6-Bus Model system showes that the voltage distribution of load buses is improved and the power loss is more reduced than before var allocation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.425-428
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• 1998

In this work, single-poly EEPROM has been designed and fabricated by using standard 0.8.mu.m CMOS process. The initial threshold voltage was aobut 0.8V but it increased ot about 6.5V after programming at Vds=11.5V and Vcg=6.5V. After erasing devices at Vs=14.2V, the threshold voltage decreased to about 1.5V. The programming time and erasing trime wree about 6ms. and 100ms. respectively. The erasing time can be reduced by applying a series of shorter erase pulse s instead of a long single erase pulse.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• 조명전기설비학회논문지
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• 제18권1호
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• pp.146-153
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• 2004

본 연구에서는 Fuzzy Goal Programming을 이용하여 배전계통에서 분산형 전원의 설치 및 운영에 대한 새로운 방안을 제시하였다. 분산형전원의 설치 및 운영을 위하여 최적화 알고리즘의 탐색공간의 크기를 줄이면서 계통상황 변동에 적합하게 정식화하였다. 특히, 목적함수인 계통 유효전력손실과 제약조건인 분산형전원의 수 또는 총용량 및 모선전압에 대하여 각각의 부정확한 성질을 평가하기 위하여 퍼지 Goal Programing으로 모델링 하였으며, 유전알고리즘을 사용하여 최적해를 탐색하였다.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 A
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• pp.262-263
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• 2006

This paper presents a scheme to solve the congestion problem with phase-shifting transformer(PST) and power generation using linear programming method. A good design of PST and power generation control can improve total transfer capability(TTC) in interconnected systems. This paper deals with an application of optimization technique for TTC calculation. linear programming method is used to maximize power flow of tie line subject to security constraints such as voltage magnitude and real power flow. The proposed method is applied to 10 machines 39 buses model systems to show its effectiveness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.15-16
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.898-901
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• 2005

We propose a novel pixel structure using bootstrapped voltage programming for amorphoussilicon TFT backplane of AM-OLED (Active Matrix-Organic Light Emitting Diode) displays. The proposed structure is composed of two TFTs and one capacitor. It operates at low drive voltage ($0{\sim}5V$) which can reduce power consumption comparing with the conventional pixel circuit structure using same OLED material. Also, it can easily control dark level and use commercial mobile LCD ICs. In this paper, we describe the operating principle and the characteristics of the proposed pixel structure and verify the performance by SPICE simulation comparing with the conventional pixel structure.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.901-904
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• 2005

A novel active matrix organic light diodes (AMOLEDs) voltage-programming pixel structure with current-correction method is proposed for largesize and high-resolution poly-Si AMOLED panel applications. The HSPICE simulation results shows that the maximum error of emission current in proposed pixel is 1.536%, 2.45%, and 2.97% with the ${\pm}12.5%$ mobility variation and ${\pm}0.3V$ threshold voltage variation for 30-, 40-, and 50-inch HDTV panels, respectively.